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參數(shù)資料
| 型號： | CYRF69213 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 64/85頁 |
| 文件大小： | 731K |
| 代理商： | CYRF69213 |
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CYRF69213
Document #: 001-07552 Rev. *B
Page 64 of 85
Mnemonic
PWR_CTRL_ADR
Address
1
0x0B
Bit
7
6
5
4
3
2
0
Default
1
0
1
-
0
0
0
0
Read/Write
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
Function
PMU EN
LVIRQ EN
PMU MODE
FORCE
Not Used
LVI TH
PMU OUTV
Bit 7
Power Management Unit (PMU) Enable. Setting this bit enables the PMU if PMU Mode Force (bit 5) is set, otherwise it has no
effect. See PMU Mode Force bit (bit 5) description.
Low Voltage Interrupt Enable. Setting this bit enables the LV IRQ interrupt. When this interrupt is enabled, if the V
BAT
voltage
falls below the threshold set by LVI TH, then a low voltage interrupt will be generated. The LVI is not available when the device
is in sleep mode. The LVI event on IRQ pin is automatically disabled whenever the PMU is disabled.
PMU Mode Force. If this bit is set, the PMU operation will be based on the value of PMU Enable bit (bit 7). If this bit is not set,
then the PMU is diabled when in Sleep mode and enabled when not in Sleep mode.
Low Voltage Interrupt Threshold. This field sets the voltage on V
BAT
at which the LVI is triggered. 11 = 1.8V, 10 = 2.0V,
01 = 2.2V, 00 = PMU OUTV voltage.
PMU Output Voltage. This field sets the minimum output voltage of the PMU. 11 = 2.4V, 10 = 2.5V, 01 = 2.6V, 00 = 2.7V. When
the PMU is active, the voltage output by the PMU on V
REG
will never be less than this voltage, provided that the total load on
the V
REG
pin is less than the specified maximum value and the voltage in V
BAT
is greater than the specified minimum value.
To force the chip to always enable the PMU (including in Sleep mode), set bit 5 and bit 7. To force the chip to always disable the PMU set bit
5 and clear bit 7. To allow the chip to disable PMU only during sleep clear bit 5.
The sequence of writing the bits in this register impact the sleep current I
SB
.
Bit 6
Bit 5
Bits 3:2
Bits 1:0
Mnemonic
XTAL_CTRL_ADR
Address
1
0x0C
Bit
7
6
5
4
3
2
0
Default
0
0
0
-
-
1
0
0
Read/Write
R/W
R/W
R/W
-
-
R/W
R/W
R/W
Function
XOUT FN
XSIRQ EN
Not Used
Not Used
FREQ
Bits 7:6
XOUT Pin Function. This field selects between the different functions of the XOUT pin. 00 = Clock frequency set by XOUT
FREQ; 01 = Active LOW PA Control; 10 = Radio data serial bit stream. If this option is selected and SPI is configured for 3-wire
mode then the MISO pin will output a serial clock associated with this data stream; 11 = GPIO. To disable this output, set to
GPIO mode, and set the GPIO state in IO_CFG_ADR.
Crystal Stable Interrupt Enable. This bit enables the OS IRQ interrupt. When enabled, this interrupt generates an IRQ event
when the crystal has stabilized after the device has woken from sleep mode. This event is cleared by writing zero to this bit.
XOUT Frequency. This field sets the frequency output on the XOUT pin when XOUT FN is set to 00. 0 = 12 MHz, 1 = 6 MHz,
2 = 3 MHz, 3 = 1.5 MHz, 4 = 0.75 MHz; other values are not defined.
Bit 5
Bits 2:0
[+] Feedback
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF69213_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69213_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69213-40LFXC | 功能描述:射頻接收器 PRoC LP COM RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| CYRF69213-40LTXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CYRF69213A-40LFXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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