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參數(shù)資料
| 型號： | CYRF69213 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 52/85頁 |
| 文件大?。?/td> | 731K |
| 代理商： | CYRF69213 |
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CYRF69213
Document #: 001-07552 Rev. *B
Page 52 of 85
Endpoint Data Buffers
The three data buffers are used to hold data for both IN and OUT transactions. Each data buffer is 8 bytes long.
The reset values of the Endpoint Data Registers are unknown.
Unlike past enCoRe parts the USB data buffers are only accessible in the I/O space of the processor.
Table 79.Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0x46] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Read/Write
Default
Bit 7
Stall
Reserved
NAK Int
Enable
R/W
0
ACK’d
Transaction
R/C (Note 3)
0
Mode[3:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Stall
When this bit is set the SIE will stall an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE will stall an IN packet if the
mode bits are set to ACK-IN. This bit must be clear for all other modes
Reserved
NAK Int Enable
This bit, when set, causes an endpoint interrupt to be generated even when a transfer completes with a NAK. Unlike enCoRe,
CYRF69213 family members do not generate an endpoint interrupt under these conditions unless this bit is set
0 = Disable interrupt on NAK’d transactions
1 = Enable interrupt on NAK’d transaction
ACK’d Transaction
The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an
ACK packet
This bit is cleared by any writes to the register
0 = The transaction does not complete with an ACK
1 = The transaction completes with an ACK
Mode [3:0]
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The mode controls how
the USB SIE responds to traffic and how the USB SIE will change the mode of that endpoint as a result of host packets to the
endpoint.
Bit 6
Bit 5
Bit 4
Bits 3:0
Note
When the SIE writes to the EP1MODE or the EP2MODE register it blocks firmware writes to the EP2MODE or the EP1MODE registers,
respectively (if both writes occur in the same clock cycle). This is because the design employs only one common ‘update’ signal for both
EP1MODE and EP2MODE registers. Thus, when SIE writes to the EP1MODE register, the update signal is set and this prevents firmware writes
to EP2MODE register. SIE writes to the endpoint mode registers have higher priority than firmware writes. This mode register write block situation
can put the endpoints in incorrect modes. Firmware must read the EP1/2MODE registers immediately following a firmware write and rewrite if
the value read is incorrect
Table 80.Endpoint 0 Data (EP0DATA) [0x50-0x57] [R/W]
Bit #
Field
Read/Write
Default
The Endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57
7
6
5
4
3
2
1
0
Endpoint 0 Data Buffer [7:0]
R/W
Unknown
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Table 81.Endpoint 1 Data (EP1DATA) [0x58-0x5F] [R/W]
Bit #
Field
Read/Write
Default
The Endpoint 1buffer is comprised of 8 bytes located at address 0x58 to 0x5F
7
6
5
4
3
2
1
0
Endpoint 1 Data Buffer [7:0]
R/W
Unknown
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
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相關代理商/技術參數(shù) |
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| CYRF69213_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69213_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
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| CYRF69213-40LTXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CYRF69213A-40LFXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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