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參數(shù)資料
| 型號： | CYRF69213 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 34/85頁 |
| 文件大?。?/td> | 731K |
| 代理商： | CYRF69213 |
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CYRF69213
Document #: 001-07552 Rev. *B
Page 34 of 85
GPIO Port Configuration
All the GPIO configuration registers have common configu-
ration controls. The following are the bit definitions of the GPIO
configuration registers.
Int Enable
When set, the Int Enable bit allows the GPIO to generate inter-
rupts. Interrupt generate can occur regardless of whether the
pin is configured for input or output. All interrupts are edge
sensitive, however for any interrupt that is shared by multiple
sources (that is, Ports 2, 3, and 4) all inputs must be
deasserted before a new interrupt can occur.
When clear, the corresponding interrupt is disabled on the pin.
It is possible to configure GPIOs as outputs, enable the
interrupt on the pin and then to generate the interrupt by
driving the appropriate pin state. This is useful in test and may
have value in applications as well.
Int Act Low
When set, the corresponding interrupt is active on the falling
edge.
When clear, the corresponding interrupt is active on the rising
edge.
TTL Thresh
When set, the input has TTL threshold. When clear, the input
has standard CMOS threshold.
High Sink
When set, the output can sink up to 50 mA.
When clear, the output can sink up to 8 mA.
On the CYRF69213, only the P1.7–P1.3 have 50-mA sink
drive capability. Other pins have 8-mA sink drive capability.
Open Drain
When set, the output on the pin is determined by the Port Data
Register. If the corresponding bit in the Port Data Register is
set, the pin is in high-impedance state. If the corresponding bit
in the Port Data Register is clear, the pin is driven low.
When clear, the output is driven LOW or HIGH.
Pull-up Enable
When set the pin has a 7K pull up to V
CC
(or VREG for ports
with V3.3 enabled).
When clear, the pull up is disabled.
Output Enable
When set, the output driver of the pin is enabled.
When clear, the output driver of the pin is disabled.
For pins with shared functions there are some special cases.
VREG Output/SPI Use
The P1.2 (VREG), P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI)
and P1.6 (SMISO) pins can be used for their dedicated
functions or for GPIO.
To enable the pin for GPIO, clear the corresponding VREG
Output or SPI Use bit. The SPI function controls the output
enable for its dedicated function pins when their GPIO enable
bit is clear.
This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register
returns the current state of the Port 1 pins
Bit 7
P1.7 Data
Bits 6:3
P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)
In addition to their use as the P1.6–P1.3 GPIOs, these pins can also be used for the alternative function as the SPI interface
pins. To configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register (
Table 51
)
The use of the pins as the P1.6–P1.3 GPIOs and the alternative functions exist in all the CYRF69213 parts
Bit 2
P1.2/VREG
A 1-
μ
F min, 2-
μ
F max capacitor is required on VREG output.
Bits 1:0
P1.1–P1.0/D– and D+
When USB mode is disabled (Bit 7 in
Table 76
is clear), the P1.1 and P1.0 bits are used to control the state of the P1.0 and
P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– and D+ pins, respectively. If the USB
Force State bit (Bit 0 in
Table 74
) is set, the state of the D– and D+ pins can be controlled by writing to the D– and D+ bits
Table 44.P1 Data Register (P1DATA) [0x01] [R/W]
Table 45.P2 Data Register (P2DATA) [0x02] [R/W]
Bit #
Field
Read/Write
Default
This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register
returns the current state of the Port 2 pins
Bits 7:2
Reserved Data [7:2]
Bits 1:0
P2 Data [1:0]
7
6
5
4
3
2
1
0
Reserved
P2.1–P2.0
-
0
-
0
-
0
-
0
-
0
-
0
R/W
0
R/W
0
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF69213_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69213_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69213-40LFXC | 功能描述:射頻接收器 PRoC LP COM RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| CYRF69213-40LTXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CYRF69213A-40LFXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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