參數(shù)資料
型號(hào): CYRF69213
廠商: Cypress Semiconductor Corp.
英文描述: Programmable Radio on Chip Low Power
中文描述: 可編程片上無線電低功耗
文件頁數(shù): 24/85頁
文件大?。?/td> 731K
代理商: CYRF69213
CYRF69213
Document #: 001-07552 Rev. *B
Page 24 of 85
Table 34.OSC Control 0 (OSC_CR0) [0x1E0] [R/W]
Bit #
7
6
5
4
Sleep Timer [1:0]
R/W
0
3
2
1
0
Field
Reserved
No Buzz
R/W
0
CPU Speed [2:0]
R/W
0
Read/Write
0
0
R/W
0
R/W
0
R/W
0
Default
Bits 7:6
Bit 5
Reserved
No Buzz
During sleep (the Sleep bit is set in the CPU_SCR Register—
Table 38
), the LVD and POR detection circuit is turned on period-
ically to detect any POR and LVD events on the V
CC
pin (the Sleep Duty Cycle bits in the ECO_TR are used to control the duty
cycle—
Table 42
). To facilitate the detection of POR and LVD events, the No Buzz bit is used to force the LVD and POR detec-
tion circuit to be continuously enabled during sleep. This results in a faster response to an LVD or POR event during sleep at the
expense of a slightly higher than average sleep current
0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle
1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled
Note
The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below
Bits 4:3
Sleep Timer [1:0]
Note
Sleep intervals are approximate
Bits 2:0
CPU Speed [2:0]
The CYRF69213 may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; therefore, the
default CPU speed is one-eighth of the internal 24 MHz, or 3 MHz
Regardless of the CPU Speed bit’s setting, if the actual CPU speed is greater than 12 MHz, the 24-MHz operating requirements
apply. An example of this scenario is a device that is configured to use an external clock, which is supplying a frequency of 20
MHz. If the CPU speed register’s value is 0b011, the CPU clock will be 20 MHz. Therefore the supply voltage requirements for
the device are the same as if the part was operating at 24 MHz. The operating voltage requirements are not relaxed until the
CPU speed is at 12 MHz or less
Important Note
Correct USB operations require the CPU clock speed be at least 1.5 MHz or not less than USB clock/8. If the two clocks have
the same source then the CPU clock divider should not be set to divide by more than 8. If the two clocks have different sources, care must be
taken to ensure that the maximum ratio of USB Clock/CPU Clock can never exceed 8 across the full specification range of both clock sources
Sleep Timer [1:0]
Sleep Timer Clock
Frequency (Nominal)
Sleep Period
(Nominal)
Watchdog Period
(Nominal)
00
512 Hz
1.95 ms
6 ms
01
64 Hz
15.6 ms
47 ms
10
8 Hz
125 ms
375 ms
11
1 Hz
1 sec
3 sec
CPU Speed [2:0]
CPU when Internal
Oscillator is selected
External Clock
000
3 MHz (Default)
Clock In/8
001
6 MHz
Clock In/4
010
12 MHz
Clock In/2
011
24 MHz
Clock In/1
100
1.5 MHz
Clock In/16
101
750 KHz
Clock In/32
110
187 KHz
Clock In/128
111
Reserved
Reserved
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