參數(shù)資料
型號(hào)： CYRF69213
廠商： Cypress Semiconductor Corp.
英文描述： Programmable Radio on Chip Low Power
中文描述： 可編程片上無線電低功耗
文件頁數(shù)： 35/85頁
文件大?。?/td> 731K
代理商： CYRF69213
CYRF69213
Document #: 001-07552 Rev. *B
Page 35 of 85
3.3V Drive
The P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6
(SMISO) pins have an alternate voltage source from the
voltage regulator. If the 3.3V Drive bit is set a high level is
driven from the voltage regulator instead of from V
CC
.
Setting the 3.3V Drive bit does not enable the voltage
regulator. That must be done explicitly by setting the VREG
Enable bit in the VREGCR Register (
Table 75
).
Figure 14. Block Diagram of a GPIO
V
CC
VREG
V
CC
VREG
GPIO
PIN
R
UP
Data Out
V
CC
GND
VREG
GND
3.3V Drive
Pull-Up Enable
Output Enable
Open Drain
Port Data
Hgh Snk
Data In
TTL Threshold
Table 46.P0.2/INT0–P0.4/INT2 Configuration (P02CR–P04CR) [0x07–0x09] [R/W]
Bit #
Field
Read/Write
Default
These registers control the operation of pins P0.2–P0.4, respectively. These pins are shared between the P0.2–P0.4 GPIOs and the INT0–INT2.
These registers exist in all CYRF69213 parts. The INT0–INT2 interrupts are different than all the other GPIO interrupts. These pins are connected
directly to the interrupt controller to provide three edge-sensitive interrupts with independent interrupt vectors. These interrupts occur on a rising
edge when Int act Low is clear and on a falling edge when Int act Low is set. These pins are enabled as interrupt sources in the interrupt controller
registers (
Table 72
and
Table 70
)
To use these pins as interrupt inputs configure them as inputs by clearing the corresponding Output Enable. If the INT0–INT2 pins are configured
as outputs with interrupts enabled, firmware can generate an interrupt by writing the appropriate value to the P0.2, P0.3 and P0.4 data bits in
the P0 Data Register
Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int act Low, TTL Threshold, Open Drain, and Pull-up Enable
bits control the behavior of the pin
The P0.2/INT0–P0.4/INT2 pins are individually configured with the P02CR (0x07), P03CR (0x08), and P04CR (0x09), respectively.
Note
Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated. When configuring these interrupt sources,
it is best to follow the following procedure:
1. Disable interrupt source
2. Configure interrupt source
3. Clear any pending interrupts from the source
4. Enable interrupt source
7
6
5
4
3
2
1
0
Reserved
Int Act Low
R/W
0
TTL Thresh
R/W
0
Reserved
–
0
Open Drain
R/W
0
Pull-up Enable Output Enable
R/W
0
–
0
–
0
R/W
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYRF69213_08 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power
CYRF69213_13 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power
CYRF69213-40LFXC 功能描述:射頻接收器 PRoC LP COM RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel
CYRF69213-40LTXC 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CYRF69213A-40LFXC 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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