參數(shù)資料
型號: CYRF69213
廠商: Cypress Semiconductor Corp.
英文描述: Programmable Radio on Chip Low Power
中文描述: 可編程片上無線電低功耗
文件頁數(shù): 36/85頁
文件大小: 731K
代理商: CYRF69213
CYRF69213
Document #: 001-07552 Rev. *B
Page 36 of 85
Table 47.P0.7 Configuration (P07CR) [0x0C] [R/W]
Bit #
Field
Read/Write
Default
This register controls the operation of pin P0.7.
7
6
5
4
3
2
1
0
Reserved
0
Int Enable
R/W
0
Int Act Low
R/W
0
TTL Thresh
R/W
0
Reserved
0
Open Drain
R/W
0
Pull-up Enable Output Enable
R/W
0
R/W
0
Table 48.P1.0/D+ Configuration (P10CR) [0x0D] [R/W]
Bit #
Field
Read/Write
Default
This register controls the operation of the P1.0 (D+) pin when the USB interface is not enabled, allowing the pin to be used as a PS2 interface
or a GPIO. See
Table 76
for information on enabling USB. When USB is enabled, none of the controls in this register have any effect on the
P1.0 pin
Note
The P1.0 is an open drain only output. It can actively drive a signal low, but cannot actively drive a signal high
Bit 1
PS/2 Pull-up Enable
0 = Disable the 5K-ohm pull-up resistors
1 = Enable 5K-ohm pull-up resistors for both P1.0 and P1.1. Enable the use of the P1.0 (D+) and P1.1 (D–) pins as a PS2 style
interface
7
6
5
4
3
2
1
0
Reserved
R/W
0
Int Enable
R/W
0
Int Act Low
R/W
0
Reserved
0
Reserved
0
Output Enable
R/W
0
0
0
Table 49.P1.1/D– Configuration (P11CR) [0x0E] [R/W]
Bit #
Field
Read/Write
Default
This register controls the operation of the P1.1 (D–) pin when the USB interface is not enabled, allowing the pin to be used as a PS2 interface
or a GPIO. See
Table 76
for information on enabling USB. When USB is enabled, none of the controls in this register have any effect on the
P1.1 pin. When USB is disabled, the 5-Kohm pull-up resistor on this pin can be enabled by the PS/2 Pull-up Enable bit of the P10CR Register
(
Table 48
)
Note
There is no 2-mA sourcing capability on this pin. The pin can only sink 5 mA at V
OL3
7
6
5
4
3
2
1
0
Reserved
0
Int Enable
R/W
0
Int Act Low
R/W
0
Reserved
Open Drain
R/W
0
Reserved
0
Output Enable
R/W
0
0
0
Table 50.P1.2 Configuration (P12CR) [0x0F] [R/W]
Bit #
Field
Read/Write
Default
This register controls the operation of the P1.2
Bit 7
CLK Output
0 = The internally selected clock is not sent out onto P1.2 pin
1 = When CLK Output is set, the internally selected clock is sent out onto P1.2 pin
7
6
5
4
3
2
1
0
CLK Output
R/W
0
Int Enable
R/W
0
Int Act Low
R/W
0
TTL Threshold
R/W
0
Reserved
0
Open Drain
R/W
0
Pull-up Enable Output Enable
R/W
0
R/W
0
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