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參數(shù)資料
| 型號(hào)： | CYP15G0101DXA-BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Single Channel HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA100 |
| 封裝： | 11 X 11 MM, 1.40 MM HEIGHT, BGA-100 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大小： | 527K |
| 代理商： | CYP15G0101DXA-BBI |
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CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 9 of 40
TRSTZ
LVTTL Input,
internal pull-up
Device Reset
. Active LOW. Initializes all state machines and counters in the device.
When sampled LOW by the rising edge of REFLCK, this input resets the internal state
machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is
removed (TRSTZ sampled HIGH by REFCLK
↑
), the status and data outputs will be-
come deterministic in less than 16 REFCLK cycles.
The BISTLE, OELE, and RXLE latches are reset by TRSTZ.
If the Elasticity Buffer or the Phase-Align Buffer are used, TRSTZ should be applied
after power up to initialize the internal pointers into these memory arrays.
Analog I/O and Control
OUT1±
CML Differential
Output
Primary Differential Serial Data Outputs
. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules. These outputs must be AC-coupled for PECL-compat-
ible connections.
Secondary Differential Serial Data Outputs
. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules. These outputs must be AC-coupled for PECL-compat-
ible connections.
Primary Differential Serial Data Inputs
. These inputs accept the serial data stream for
deserialization and decoding. The IN1±
serial stream is passed to the receiver Clock
and Data Recovery (CDR) circuit to extract the data content when INSEL = HIGH.
Secondary Differential Serial Data Inputs
. These inputs accept the serial data stream
for deserialization and decoding. The IN2±
serial stream is passed to the receiver Clock
and Data Recovery (CDR) circuit to extract the data content when INSEL = LOW.
Receive Input Selector
. Determines which external serial bit stream is passed to the
receiver Clock and Data Recovery circuit. When HIGH, the IN1± input is selected. When
LOW, the IN2
±
input is selected.
Signal Detect Amplitude Level Select
. Allows selection of one of three predefined
amplitude trip points for a valid signal indication, as listed in
Table 10
.
Loop-Back-Enable
. Active HIGH. When asserted (HIGH), the transmit serial data is
internally routed to the receiver Clock and Data Recovery (CDR) circuit. All enabled
serial drivers are forced to differential logic
“
1
”
. All serial data inputs are ignored.
Serial Driver Output Enable Latch Enable
. Active HIGH. When OELE = HIGH, the
signals on the BOE[1:0] inputs directly control the OUTxy± differential drivers. When the
BOE[x] input is HIGH, the associated OUTx± differential driver is enabled. When the
BOE[x] input is LOW, the associated OUTx± differential driver is powered down. When
OELE returns LOW, the last values present on BOE[1:0] are captured in the internal
Output Enable Latch. The specific mapping of BOE[1:0] signals to transmit output en-
ables is listed in
Table 8
.
If the device is reset (TRSTZ is sampled LOW), the latch is reset to disable both outputs.
Transmit and Receive BIST Latch Enable
. Active HIGH. When BISTLE = HIGH, the
signals on the BOE[1:0] inputs directly control the transmit and receive BIST enables.
When the BOE[x] input is LOW, the associated transmit or receive channel is configured
to generate or compare the BIST sequence. When the BOE[x] input is HIGH, the asso-
ciated transmit or receive channel is configured for normal data transmission or recep-
tion. When BISTLE returns LOW, the last values present on BOE[1:0] are captured in
the internal BIST Enable latch. The specific mapping of BOE[1:0] signals to transmit and
receive BIST enables is listed in
Table 8
.
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is
reset to disable BIST on both the transmit and receive channels.
OUT2±
CML Differential
Output
IN1±
LVPECL Differential
Input
IN2±
LVPECL Differential
Input
INSEL
LVTTL Input,
asynchronous
SDASEL
3-Level Select
[2]
,
static control input
LVTTL Input,
asynchronous,
internal pull-down
LVTTL Input,
asynchronous,
internal pull-up
LPEN
OELE
BISTLE
LVTTL Input,
asynchronous,
internal pull-up
Pin Descriptions
(continued)
CYP15G0101DXA Single Channel HOTLink II
Transceiver
Name
I/O Characteristics
Signal Description
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PDF描述 |
|---|---|
| CYP15G0402DX-BGC | Quad HOTLinkII SERDES |
| CYP15G0402DX | Quad HOTLinkII SERDES |
| CYP15G0402DX-BGI | Quad HOTLinkII SERDES |
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0101DXB-BBI | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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