參數(shù)資料
型號(hào)： CYP15G0101DXA-BBI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Single Channel HOTLink II Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA100
封裝： 11 X 11 MM, 1.40 MM HEIGHT, BGA-100
文件頁(yè)數(shù)： 17/40頁(yè)
文件大?。?/td> 527K
代理商： CYP15G0101DXA-BBI
CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 17 of 40
aries. When RFEN = HIGH, the Framer-mode selected by RF-
MODE is enabled.
When RFMODE = LOW, the Low-Latency Framer is selected.
This Framer operates by stretching the recovered character
clock until it aligns with the received character boundaries. In
this mode the Framer starts its alignment process on the first
detection of the selected framing character. To reduce the im-
pact on external circuits that make use of a recovered clock,
the clock period is not stretched by more than two bit-periods
in any one clock cycle. When operated with a character-rate
output clock (RXRATE = LOW), the output of properly framed
characters may be delayed by up to nine character-clock cy-
cles from the detection of the selected framing character.
When operated with a half-character-rate output clock
(RXRATE = HIGH), the output of properly framed characters
may be delayed by up to 14 character-clock cycles from the
detection of the selected framing character.
NOTE:
When Receive BIST is enabled on a channel, the
Low-Latency Framer must not be enabled. The BIST se-
quence contains an aliased K28.5 framing character, which
would cause the Receiver to update its character bound-
aries incorrectly.
When RFMODE = MID (open) the Cypress-mode multi-byte
Framer is selected. The required detection of multiple framing
characters makes the link much more robust to incorrect fram-
ing due to aliased SYNC characters in the data stream. In this
mode, the Framer does not adjust the character clock bound-
ary, but instead aligns the character to the already recovered
character clock. This ensures that the recovered clock does
not contain any significant phase changes or hops during nor-
mal operation or framing, and allows the recovered clock to be
replicated and distributed to other external circuits or compo-
nents using PLL-based clock distribution elements. In this
framing mode the character boundaries are only adjusted if the
selected framing character is detected at least twice within a
span of 50 bits, with both instances on identical 10-bit charac-
ter boundaries.
When RFMODE = HIGH, the Alternate-mode multi-byte
Framer is enabled. Like the Cypress-mode multi-byte Framer,
multiple framing characters must be detected before the char-
acter boundary is adjusted. In this mode, the data stream must
contain a minimum of four of the selected framing characters,
received as consecutive characters, on identical 10-bit bound-
aries, before character framing is adjusted.
Framing is enabled when RFEN = HIGH. If RFEN = LOW, the
Framer is disabled. When the Framer is disabled, no changes
are made to the recovered character boundary, regardless of
the presence of framing characters in the data stream.
10B/8B Decoder Block
The Decoder logic block performs three primary functions:
decoding the received transmission characters back into
Data and Special Character codes,
comparing generated BIST patterns with received charac-
ters to permit at-speed link and device testing,
and generation of ODD parity on the decoded characters.
10B/8B Decoder
The framed parallel output of the Deserializer Shifter is passed
to the 10B/8B Decoder where, if the Decoder is enabled
(DECMODE
≠
LOW), it is transformed from a 10-bit transmis-
sion character back to the original Data and Special Character
codes. This block uses the 10B/8B Decoder patterns in
Table 21
and
Table 22
of this data sheet. Valid data characters
are indicated by a 000b bit-combination on the RXST[2:0] sta-
tus bits, and Special Character codes are indicated by a 001b bit-
combination on these same status outputs. Framing characters,
invalid patterns, disparity errors, and synchronization status are pre-
sented as alternate combinations of these status bits.
The 10B/8B Decoder operates in two normal modes, and can
also be bypassed. The operating mode for the Decoder is con-
trolled by the DECMODE input.
When DECMODE = LOW, the Decoder is bypassed and raw
10-bit characters are passed to the Output Register. In this
mode, the receive Elasticity Buffers are bypassed, and RXCK-
SEL must be MID. This clock mode generates separate RX-
CLK
±
outputs for the receive channel.
When DECMODE = MID (or open), the 10-bit transmission
characters are decoded using
Table 21
and
Table 22
. Re-
ceived Special Code characters are decoded using the Cy-
press column of
Table 22
.
When DECMODE = HIGH, the 10-bit transmission characters
are decoded using
Table 21
and
Table 22
. Received Special
Code characters are decoded using the Alternate column of
Table 22
.
Receive BIST Operation
The Receiver interface contains an internal pattern generator
that can be used to validate both device and link operation.
This generator is enabled by the BOE[0] signal as listed in
Table 8
(when the BISTLE latch enable input is HIGH). When
enabled, a register in the Receive channel becomes a pattern
generator and checker by logically converting to a Linear
Feedback Shift Register (LFSR). This LFSR generates a 511-
character sequence that includes all Data and Special Char-
acter codes, including the explicit violation symbols. This pro-
vides a predictable yet pseudo-random sequence that can be
matched to an identical LFSR in the attached Transmitter.
When synchronized with the received data stream, the Receiv-
er checks each character in the Decoder with each character
generated by the LFSR and indicates compare errors and
BIST status at the RXST[2:0] bits of the Output Register.
When the BISTLE signal is HIGH, if the BOE[0] input is LOW
the BIST generator/checker in the Receive channel is enabled
(and if BOE[1] = LOW the BIST generator in the transmit chan-
nel is enabled). When BISTLE returns LOW, the values of the
BOE[1:0] signals are captured in the BIST Enable Latch.
These values remain in the BIST Enable Latch until BISTLE is
returned high to open the latch again. All captured signals in
the BIST Enable Latch are set HIGH (i.e., BIST is disabled)
following a device reset (TRSTZ is sampled LOW).
When BIST is first recognized as being enabled in the Receiv-
er, the LFSR is preset to the BIST-loop start-code of D0.0. This
D0.0 character is sent only once per BIST loop. The status of
the BIST progress and any character mismatches is presented
on the RXST[2:0] status outputs.
Code rule violations or running disparity errors that occur as
part of the BIST loop do not cause an error indication.
RXST[2:0] indicates 010b or 100b for one character period per
BIST loop to indicate loop completion. This status can be used to
check test pattern progress. These same status values are present-
ed when the Decoder is bypassed and BIST is enabled on the
Receive channel.
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