參數(shù)資料
型號(hào)： CYP15G0101DXA-BBI
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Single Channel HOTLink II Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA100
封裝： 11 X 11 MM, 1.40 MM HEIGHT, BGA-100
文件頁(yè)數(shù)： 14/40頁(yè)
文件大?。?/td> 527K
代理商： CYP15G0101DXA-BBI
CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 14 of 40
When TXCKSEL = LOW, the Input Register for the transmit
channel is clocked by REFCLK
[1]
. When TXCKSEL = HIGH,
the Input Register for the transmit channel is clocked with
TXCLK
↑
.
TX Mode 4
—
Atomic Word Sync and SCSEL Control of
Word Sync Sequence Generation
When configured in TX Mode 4, the SCSEL input is captured
along with the TXCT[1:0] data control inputs. These bits com-
bine to control the interpretation of the TXD[7:0] bits and the
characters generated by them. These bits are interpreted as
listed in
Table 6
.
TX Mode 4 also supports an Atomic Word Sync Sequence.
Unlike TX Mode 3, this sequence is started when both SCSEL
and TXCT[0] are sampled HIGH. With the exception of the
combination of control bits used to initiate the sequence, the
generation and operation of this Word Sync Sequence is the
same as that documented for TX Mode 3.
TX Mode 5
—
Atomic Word Sync, No SCSEL
When configured in TX Mode 5, the SCSEL signal is not used.
The TXCT[1:0] inputs control the characters generated by the
channel. The specific characters generated by these bits are
listed in
Table 7
.
TX Mode 5 also has the capability of generating an Atomic
Word Sync Sequence. For the sequence to be started, the
TXCT[1:0] inputs must both be sampled HIGH. The generation
and operation of this Word Sync Sequence is the same as that
documented for TX Mode 3.
Transmit BIST
The transmit channel contains an internal pattern generator
that can be used to validate both device and link operation.
This generator is enabled by the BOE[1] signal, as listed in
Table 8
(when the BISTLE latch enable input is HIGH). When
enabled, a register in the transmit channel becomes a signa-
ture pattern generator by logically converting to a Linear Feed-
back Shift Register (LFSR). This LFSR generates a 511-char-
acter sequence that includes all Data and Special Character
codes, including the explicit violation symbols. This provides a
predictable yet pseudo-random sequence that can be
matched to an identical LFSR in the attached Receiver.
When the BISTLE signal is HIGH, if the BOE[1] input is LOW
the BIST generator in the transmit channel is enabled (and if
BOE[0] = LOW the BIST checker in the receive channel is en-
abled). When BISTLE returns LOW, the values of the BOE[1:0]
signals are captured in the BIST Enable Latch. These values
remain in the BIST Enable Latch until BISTLE is returned high
to open the latch again. A device reset (TRSTZ sampled
LOW), also presets the BIST Enable Latch to disable BIST on
both the transmit and receive channels.
All data and data-control information present at the TXD[7:0]
and TXCT[1:0] inputs are ignored when BIST is active on the
transmit channel. If the receive channel is configured for com-
mon clock operation (RXCKSEL = LOW) each pass is preced-
ed by a 16-character Word Sync Sequence to allow Elasticity
Buffer alignment and management of clock-frequency varia-
tions.
Serial Output Drivers
The serial interface Output Drivers use high-performance dif-
ferential CML (Current Mode Logic) to provide source-
matched drivers for the transmission lines. These Serial Driv-
ers accept data from the Transmit Shifter. These outputs have
signal swings equivalent to that of standard PECL drivers, and
are capable of driving AC-coupled optical modules or AC-cou-
pled transmission lines.
When configured for local loopback (LPEN = HIGH), the en-
abled Serial Drivers are configured to drive a static differential
logic-1.
Each Serial Driver can be enabled or disabled through the
BOE[1:0] inputs, as controlled by the OELE latch-enable sig-
nal. When OELE = HIGH, the signals present on the BOE[1:0]
inputs are passed through the Serial Output Enable latch to
control the Serial Driver. The BOE[1:0] input with OUT1
±
and
OUT2
±
driver is listed in
Table 8
.
When OELE = HIGH and BOE[x] = HIGH, the associated Se-
rial Driver is enabled to drive any attached transmission line.
When OELE = HIGH and BOE[x] = LOW, the associated driv-
er is disabled and internally configured for minimum power
dissipation. If both Serial Drivers for the channel are disabled,
the internal logic for the channel is also configured for lowest
power operation. When OELE returns LOW, the values
present on the BOE[1:0] inputs are latched in the Output En-
able Latch, and remain there until OELE returns HIGH to open
the latch again. A device reset (TRSTZ sampled LOW) clears
this latch and disables both Serial Drivers.
Table 6. TX Modes 4 and 7 Encoding
S
T
T
Characters Generated
Encoded data character
K28.5 fill character
Special character code
16-character Word Sync Sequence
X
0
0
1
X
0
1
X
0
1
1
1
Table 7. TX Modes 5 and 8 Encoding
S
T
T
0
1
0
1
Characters Generated
Encoded data character
K28.5 fill character
Special character code
16-character Word Sync Sequence
X
X
X
X
0
0
1
1
Table 8. Output Enable, BIST, and Receive Channel
Enable Signal Map
BOE
Input
BOE[1]
BOE[0]
Output
Controlled
(OELE)
OUT2
±
OUT1
±
BIST
Channel
Enable
(BISTLE)
Transmit
Receive
Receive PLL
Channel
Enable
(RXLE)
X
Receive
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