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參數(shù)資料
| 型號： | CYP15G0101DXA-BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Single Channel HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA100 |
| 封裝： | 11 X 11 MM, 1.40 MM HEIGHT, BGA-100 |
| 文件頁數(shù)： | 10/40頁 |
| 文件大?。?/td> | 527K |
| 代理商： | CYP15G0101DXA-BBI |
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CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 10 of 40
RXLE
LVTTL Input,
asynchronous,
internal pull-up
Receive Channel Power-Control Latch Enable
. Active HIGH. When RXLE = HIGH,
the signal on the BOE[0] input directly controls the power enable for the receive PLL
and analog logic. When the BOE[0] input is HIGH, the receive channel PLL and analog
logic are active. When the BOE[0] input is LOW, the receive channel PLL and analog
logic are placed in a non-functional power saving mode. When RXLE returns LOW, the
last value present on BOE[0] is captured in the internal RX PLL Enable latch. The
specific mapping of BOE[1:0] signals to the receive channel enable is listed in
Table 8
.
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is
reset to disable the receive channel.
BIST, Serial Output, and Receive Channel Enables
.
These inputs are passed to and through the output enable latch when OELE = HIGH,
and captured in this latch when OELE returns LOW.
These inputs are passed to and through the BIST enable latch when BISTLE = HIGH,
and captured in this latch when BISTLE returns LOW.
These inputs are passed to and through the Receive Channel enable latch when
RXLE = HIGH, and captured in this latch when RXLE returns LOW.
Link Fault Indication Output
. Active LOW. LFI is the logical OR of four internal condi-
tions:
1. Received serial data frequency outside expected range
2. Analog amplitude below expected levels
3. Transition density lower than expected
4. Receive Channel disabled
BOE[1:0]
LVTTL Input,
asynchronous,
internal pull-up
LFI
LVTTL Output,
synchronous to the
selected RXCLK
↑
output or
REFCLK
↑
[1]
input,
asynchronous to
receive channel
enable/disable
Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select
. Used to control access to the JTAG Test Modes. If maintained high
for >5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset
automatically upon application of power to the device.
JTAG Test Clock
TCLK
LVTTL Input,
internal pull-down
Three-State
LVTTL Output
LVTTL Input,
internal pull-up
LVTTL Input, internal
pull-up
TDO
Test Data Out
. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
Test Data In
. JTAG data input port.
TDI
TSTCLK
Test Clock Input
. For internal use. Tie HIGH for normal operation
Power
V
CC
GND
+3.3V Power
Signal and Power Ground for all internal circuits
Pin Descriptions
(continued)
CYP15G0101DXA Single Channel HOTLink II
Transceiver
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0402DX-BGC | Quad HOTLinkII SERDES |
| CYP15G0402DX | Quad HOTLinkII SERDES |
| CYP15G0402DX-BGI | Quad HOTLinkII SERDES |
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0101DXB-BBI | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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