參數(shù)資料
型號(hào)： CYP15G0101DXA-BBI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Single Channel HOTLink II Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA100
封裝： 11 X 11 MM, 1.40 MM HEIGHT, BGA-100
文件頁(yè)數(shù)： 19/40頁(yè)
文件大?。?/td> 527K
代理商： CYP15G0101DXA-BBI
CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 19 of 40
abled. When a BOE[1:0] input is LOW, the associated Serial
Driver is disabled. When OELE returns LOW, the values
present on the BOE[1:0] inputs are latched in the Output En-
able Latch.
Device Reset State
When the CYP15G0101DXA is reset by assertion of TRSTZ,
both the Transmit Enable and Receive Enable Latches are
cleared, and the BIST Enable Latch is preset. In this state, the
Transmit and Receive channels are disabled, and BIST is dis-
abled.
Following a device reset, it is necessary to enable the transmit
and receive channels for normal operation. This can be done
by sequencing the appropriate values on the BOE[1:0] inputs
while the OELE and RXLE signals are raised and lowered. For
systems that do not require dynamic control of power, or want
the part to power up in a fixed configuration, it is also possible
to strap the RXLE and OELE control signals HIGH to perma-
nently enable their associated latches. Connection of the as-
sociated BOE[1:0] signals HIGH will then enable the Transmit
and Receive channels as soon as the TRSTZ signal is deas-
serted.
Output Bus
The receive channel presents a 12-signal output bus consist-
ing of
an 8-bit data bus
a 3-bit status bus
a parity bit
The signals present on this output bus are modified by the
present operating mode of the CYP15G0101DXA as selected
by DECMODE. This mapping is shown in
Table 14
.
When the 10B/8B Decoder is bypassed (DECMODE = LOW),
the framed 10-bit character and a single status bit are present-
ed to the receiver Output Register, along with a status output
indicating if the character in the Output Register is one of the
selected framing characters. The bit usage and mapping of the
external signals to the raw 10B transmission character is
shown in
Table 15
.
The COMDET status output operates the same regardless of
the bit combination selected for character framing by the
FRAMCHAR input. It is HIGH when the character in the Output
Register contains the selected framing character at the proper
character boundary, and LOW for all other bit combinations.
When the Low-Latency Framer and half-rate receive port
clocking is also enabled (RFMODE = LOW, RXRATE = HIGH,
and RXCKSEL = MID), the Framer will stretch the recovered
clock to the nearest 20-bit boundary such that the rising edge
of RXCLK+ occurs when COMDET = HIGH in the Output Reg-
ister.
When the Cypress or Alternate-mode Framer is enabled and
half-rate
receive
port
clocking
(RFMODE
≠
LOW and RXRATE = HIGH), the output clock is
not modified when framing is detected, but a single pipeline
stage may be added or subtracted from the data stream by the
Framer logic such that the rising edge of RXCLK+ occurs
when COMDET = HIGH in the Output Register.
This adjustment only occurs when the Framer is enabled
(RFEN = HIGH). When the Framer is disabled, the clock
boundaries are not adjusted, and COMDET may be asserted
during the rising edge of RXCLK
–
(if an odd number of char-
acters were received following the initial framing).
is
also
enabled
Parity Generation
In addition to the eleven data and status bits that are present-
ed, an RXOP parity output is also available. This allows the
CYP15G0101DXA to support ODD parity generation. To han-
dle
a
wide
range
of
CYP15G0101DXA supports multiple different forms of parity
generation (in addition to no parity). When the Decoder is en-
abled (DECMODE
≠
LOW), parity can be generated on
the RXD[7:0] character
the RXD[7:0] character and RXST[2:0] status
When the Decoder is bypassed (DECMODE = LOW), parity
can be generated on
the RXD[7:0] and RXST[1:0] bits
the RXD[7:0] and RXST[2:0] bits
These modes differ in the number bits which are included in
the parity calculation. For all cases, only ODD parity is provid-
ed which ensures that at least one bit of the data bus is always
a logic-1. Those bits covered by parity generation are listed in
Table 16
.
system
environments,
the
Table 14. Output Register Bit Assignments
[8]
Signal Name
RXST[2]
(LSB)
RXST[1]
RXST[0]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
RXD[6]
RXD[7]
(MSB)
DECMODE
=
LOW
COMDET
DOUT[0]
DOUT[1]
DOUT[2]
DOUT[3]
DOUT[4]
DOUT[5]
DOUT[6]
DOUT[7]
DOUT[8]
DOUT[9]
DECMODE
=
MID
or HIGH
RXST[2]
RXST[1]
RXST[0]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
RXD[6]
RXD[7]
Note:
8.
The RXOP output is also driven from the Output Register, but its inter-
pretation is under the separate control of PARCTL.
Table 15. Decoder Bypass Mode (DECMODE
=
LOW)
Signal Name
RXST[2]
(LSB)
RXST[1]
RXST[0]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
RXD[6]
RXD[7]
(MSB)
Bus Weight
COMDET
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
10B Name
a
b
c
d
e
i
f
g
h
j
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