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參數資料
| 型號： | CYP15G0101DXA-BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Single Channel HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA100 |
| 封裝： | 11 X 11 MM, 1.40 MM HEIGHT, BGA-100 |
| 文件頁數： | 20/40頁 |
| 文件大?。?/td> | 527K |
| 代理商： | CYP15G0101DXA-BBI |
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CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 20 of 40
Parity generation is enabled through the 3-level select
PARCTL input. When PARCTL = LOW, parity checking is dis-
abled, and the RXOP output is disabled (High-Z).
When PARCTL = MID (open) and the Decoder is enabled
(DECMODE
≠
LOW), ODD parity is generated for the received
and decoded character in the RXD[7:0] signals and is present-
ed on the RXOP output.
When PARCTL = MID (open) and the Decoder is bypassed
(DECMODE = LOW), ODD parity is generated for the received
and decoded character in the RXD[7:0] and RXST[1:0] bit po-
sitions.
When PARCTL = HIGH, ODD parity is generated for the
TXD[7:0] and the RXST[2:0] status bits.
When the Output Register clocking is such that the decoded
character is passed through the receive Elasticity Buffer prior
to the addition of the RXST[2:0] status bits, the output parity
calculation becomes a two-step process. The first parity calcu-
lation takes place as soon as the character is framed and de-
coded. This generates proper parity for the data portion of the
decoded character which is then written to the Elasticity Buffer.
If the parity calculation also includes the RXST[2:0] status bits
(PARCTL = HIGH), a second parity calculation is made prior
to loading the data and status bits into the receive Output Reg-
ister. This is necessary because the status bits with a charac-
ter in the Output Register are not necessarily determined until
after the character is read from the receive Elasticity Buffer.
This second parity calculation is based only on the content of
the status bits, and the singular parity bit associated with the
character read from the Elasticity Buffer.
Receive Status Bits
When the 10B/8B Decoder is enabled (DECMODE
≠
LOW),
each character presented at the Output Register includes
three associated status bits. These bits are used to identify
if the contents of the data bus are valid,
the type of character present,
the state of receive BIST operations (regardless of the state
of DECMODE),
character violations.
These conditions normally overlap; e.g., a valid data character
received with incorrect running disparity is not reported as a
valid data character. It is instead reported as a Decoder viola-
tion of some specific type. This implies a hierarchy or priority
level to the various status bit combinations. The hierarchy and
value of each status is listed in
Table 17
.
Within these status decodes, there are three forms of status
reporting. The two normal or data status reporting modes
(Type A and Type B) are selectable through the RXMODE in-
put. These status types allow compatibility with legacy sys-
tems, while allowing full reporting in new systems. The third
status type is used for reporting receive BIST status and
progress.
BIST Status State Machine
When the receive path is enabled to look for and compare the
received data stream with the BIST pattern, the RXST[2:0] bits
identify the present state of the BIST compare operation.
The BIST state machine has multiple states, as shown in
Figure 2
and
Table 17
. When the receive PLL detects an out-
of-lock condition, the BIST state is forced to the Start-of-BIST
state, regardless of the present state of the BIST state ma-
chine. If the number of detected errors ever exceeds the num-
ber of valid matches by greater than 16, the state machine is
forced to the WAIT_FOR_BIST state where it monitors the in-
terface for the first character (D0.0) of the next BIST se-
quence. Also, if the Elasticity Buffer ever hits and overflow/un-
derflow condition, the status is forced to the BIST_START until
the buffer is re-centered (approximately nine character peri-
ods).
To ensure compatibility between the source and destination
systems when operating in BIST, the sending and receiving
ends of the BIST sequence must use the same clock set-up
(RXCKSEL = MID or RXCKSEL = LOW).
JTAG Support
The CYP15G0101DXA contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, only boundary scan is supported. This capability is
present only on the LVTTL inputs and outputs and the REF-
CLK
±
clock input. The high-speed serial inputs and outputs are
not part of the JTAG test chain.
JTAG ID
The JTAG device ID for the CYP15G0101DXA is
‘
0C800069
’
x.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan reg-
ister. These bits report the LOW, MID, and HIGH state of the
associated input as 00, 10, and 11 respectively.
Table 16. Output Register Parity Generation
Signal
Name
RXST[2]
RXST[1]
RXST[0]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
RXD[6]
RXD[7]
Receive Parity Generate Mode (PARCTL)
LOW
[9]
MID
DECMODE
= LOW
HIGH
DECMODE
≠
LOW
X
[10]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Notes:
9.
Receive path parity output drivers (RXOPx) are disabled (High-Z) when
PARCTL
=
LOW
10. When the Decoder is bypassed (DECMODE
=
LOW) and BIST is not
enabled (Receive BIST Latch output is HIGH), RXSTx[2] is driven to a
logic-0, except when the character in the output buffer is a framing char-
acter.
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|---|---|
| CYP15G0402DX-BGC | Quad HOTLinkII SERDES |
| CYP15G0402DX | Quad HOTLinkII SERDES |
| CYP15G0402DX-BGI | Quad HOTLinkII SERDES |
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉換器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0101DXB-BBI | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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