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參數(shù)資料
| 型號： | CYP15G0101DXA-BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Single Channel HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA100 |
| 封裝： | 11 X 11 MM, 1.40 MM HEIGHT, BGA-100 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 527K |
| 代理商： | CYP15G0101DXA-BBI |
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CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 7 of 40
RXOP
3-state, LVTTL
Output, synchronous
to the
RXCLK
↑
output or
REFCLK
↑
[1]
input
Receive Path Odd Parity
. When parity generation is enabled (PARCTL
≠
LOW), the
parity output is valid for the data on the RXD bus bits. When parity generation is disabled
(PARCTL = LOW) this output driver is disabled (High-Z).
Receive Path Clock and Clock Control
RXRATE
LVTTL Input
Static Control Input,
internal pull-down
Receive Clock Rate Select
.
When LOW, the RXCLK
±
recovered clock outputs are complementary clocks operating
at the recovered character rate. Data for the receive channel should be latched on either
the rising edge of RXCLK+ or falling edge of RXCLK
–
.
When HIGH, the RXCLK
±
recovered clock outputs are complementary clocks operating
at half the character rate. Data for the receive channel should be latched alternately on
the rising edge of RXCLK+ and RXCLK
–
.
When operated with REFCLK clocking of the received parallel data outputs
(RXCKSEL = LOW), RXRATE must be LOW.
Receive Character Clock Output or Clock Select Input
. When the receive Elasticity
Buffer is disabled (RXCKSEL = MID), this true and complement clock is the Receive
Interface Clock. This is used to control timing of data output transfers. This clock is
output continuously at either the dual-character rate (1/20
th
the serial bit-rate) or char-
acter rate (1/10
th
the serial bit-rate) of the data being received, as selected by RXRATE.
When configured such that all output data path is clocked by REFCLK instead of a
recovered clock (RXCKSEL = LOW), the RXCLK
±
and RXCLKC
+
output drivers
present a buffered form of REFCLK. RXCLK
±
and RXCLKC
+
are buffered forms of
REFCLK that are slightly different in phase. This phase difference allows the user to
select the optimal setup/hold timing for their specific interface.
Received Character Clock Output Delayed
.
When configured such that the output data path is clocked by REFCLK instead of a
recovered clock (RXCKSEL = LOW), the RXCLKC+ output driver presents a buffered
form of REFCLK that is slightly different in phase from RXCLK
±
. This phase difference
allows the user to select the optimal setup/hold timing for their specific interface.
Reframe Enable
. Active HIGH. When HIGH, the Framer in the receive channel is en-
abled to frame per the presently enabled framing mode and selected framing character.
RXCLK
±
3-state, LVTTL
Output clock
RXCLKC+
3-state, LVTTL
Output clock
RFEN
LVTTL input,
asynchronous,
internal pull-down
3-Level Select
[2]
static control input
RXMODE
Receive Operating Mode
. This input selects one of two RXST channel status reporting
modes and is only interpreted when the Decoder is enabled (DECMODE
≠
LOW). See
Table 13
for details.
Receive Clock Mode
. Selects the receive clock source used to transfer data to the
Output Registers and configures the Elasticity Buffer in the receive path.
When LOW, the Output Register is clocked by REFCLK. RXCLK
±
and RXCLKC+
present buffered and delayed forms of REFCLK.
When MID, the RXCLK
±
output follows the recovered clock as selected by RXRATE
and the Elasticity Buffer is bypassed.
HIGH is an invalid state for this input.
Framing Character Select
. Used to select the character or portion of a character used
for character framing of the received data streams.
When MID, the Framer looks for both positive and negative disparity versions of the 8-
bit Comma character.
When HIGH, the Framer looks for both positive and negative disparity versions of the
K28.5 character.
The LOW selection is reserved for component test.
RXCKSEL
3-Level Select
[2]
static control input
FRAMCHAR
3-Level Select
[2]
static control input
Pin Descriptions
(continued)
CYP15G0101DXA Single Channel HOTLink II
Transceiver
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0402DX-BGC | Quad HOTLinkII SERDES |
| CYP15G0402DX | Quad HOTLinkII SERDES |
| CYP15G0402DX-BGI | Quad HOTLinkII SERDES |
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0101DXB-BBI | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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