- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380224 > CYP15G0101DXA-BBI (CYPRESS SEMICONDUCTOR CORP) Single Channel HOTLink II Transceiver PDF資料下載
參數(shù)資料
| 型號： | CYP15G0101DXA-BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Single Channel HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA100 |
| 封裝： | 11 X 11 MM, 1.40 MM HEIGHT, BGA-100 |
| 文件頁數(shù)： | 8/40頁 |
| 文件大?。?/td> | 527K |
| 代理商： | CYP15G0101DXA-BBI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 8 of 40
RFMODE
3-Level Select
[2]
static control input
Reframe Mode Select
. Used to select the type of character framing used to adjust the
character boundaries (based on detection of one or more framing characters in the data
stream. This signal operates in conjunction with the type of framing character selected.
When LOW, the Low-Latency Framer is selected. This will frame on each occurrence
of the selected framing character(s) in the received data stream. This mode of framing
stretches the recovered clock for one or multiple cycles to align that clock with the
recovered data.
When MID, the Cypress-mode multi-byte parallel Framer is selected. This requires a
pair of the selected framing character(s), on identical 10-bit boundaries, within a span
of 50 bits, before the character boundaries are adjusted. The recovered character clock
remains in the same phasing regardless of character offset.
When HIGH, the Alternate-mode multi-byte parallel Framer is selected. This requires
detection of the selected framing character(s) of the allowed disparities in the received
data stream, on identical 10-bit boundaries, on four directly adjacent characters. The
recovered character clock remains in the same phasing regardless of character offset.
Decoder Mode Select
.
When LOW, the Decoder is bypassed and raw 10-bit characters are passed to the
Output Register.
When MID, the Cypress Decoder table for Special Code Characters is used.
When HIGH, the alternate Decoder table for Special Code Characters is used. See
Table 22
for a list of the Special Codes supported in both encoded modes.
DECMODE
3-Level Select
[2]
static control input
Device Control Signals
PARCTL
3-Level Select
[2]
static control input
Parity Check/Generate Control
. Used to control the parity check and generate func-
tions.
When LOW, parity checking is disabled, and the RXOP output is disabled (High-Z).
When MID, and the 8B/10B Encoder and Decoder are enabled (TXMODE[1]
≠
LOW,
DECMODE
≠
LOW), TXD[7:0] inputs are checked (along with TXOP) for valid ODD
parity, and ODD parity is generated for the RXD[7:0] outputs and presented on RXOP.
When the 8B/10B Encoder and Decoder are disabled (TXMODE[1]
=
LOW,
DECMODE
=
LOW), the TXD[7:0] and TXCT[1:0] inputs are checked (along with TXOP)
for valid ODD parity, and ODD parity is generated for the RXD[7:0] and RXST[1:0]
outputs and presented on RXOP.
When HIGH, parity generation and checking are enabled. The TXD[7:0] and TXCT[1:0]
inputs are checked (along with TXOP) for valid ODD parity, and ODD parity is generated
for the RXD[7:0] and RXST[2:0] outputs and presented on RXOP.
Serial Rate Select. This input specifies the operating bit-rate range of both transmit and
receive PLLs. LOW = 200
–
400 MBd, MID = 400
–
800 MBd, HIGH = 800
–
1500 MBd.
Reference Clock. This clock input is used as the timing reference for the transmit and
receive PLLs. This input clock may also be selected to clock the transmit and receive
parallel interfaces. When driven by a single-ended LVCMOS or LVTTL clock source,
connect the clock source to either the true or complement REFCLK input, and leave the
alternate REFCLK input open (floating). When driven by an LVPECL clock source, the
clock must be a differential clock, using both inputs.
When TXCKSEL = LOW, REFCLK is also used as the clock for the parallel transmit data
(input) interface.
When RXCKSEL = LOW, REFCLK is also used as the clock source for the parallel
receive data (output) interface.
SPDSEL
3-Level Select
[2]
,
static control input
Differential LVPECL
or single-ended
LVTTL input clock
REFCLK±
Pin Descriptions
(continued)
CYP15G0101DXA Single Channel HOTLink II
Transceiver
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0402DX-BGC | Quad HOTLinkII SERDES |
| CYP15G0402DX | Quad HOTLinkII SERDES |
| CYP15G0402DX-BGI | Quad HOTLinkII SERDES |
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0101DXB-BBI | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。