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參數(shù)資料
| 型號(hào)： | CYP15G0101DXA-BBI |
| 廠(chǎng)商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Single Channel HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA100 |
| 封裝： | 11 X 11 MM, 1.40 MM HEIGHT, BGA-100 |
| 文件頁(yè)數(shù)： | 26/40頁(yè) |
| 文件大小： | 527K |
| 代理商： | CYP15G0101DXA-BBI |
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CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 26 of 40
CYP15G0101DXA REFCLK Switching Characteristics
Over the Operating Range
Parameter
Description
Min.
Max.
Unit
f
REF
t
REFCLK
t
REFH
REFCLK Clock Frequency
20
150
MHz
REFCLK Period
6.6
50
ns
REFCLK HIGH Time (TXRATE = HIGH)
5.9
2.9
[17]
ns
REFCLK HIGH Time (TXRATE = LOW)
ns
t
REFL
REFCLK LOW Time (TXRATE = HIGH)
5.9
2.9
[17]
ns
REFCLK LOW Time (TXRATE = LOW)
ns
t
REFD[23]
t
REFR[17, 20, 21]
t
REFF[17, 20, 21]
t
TREFDS
t
TREFDH
t
RREFDA
t
RREFDV
t
RREFADV
–
t
RREFADV+
t
RREFCDV
–
t
RREFCDV+
t
REFRX
REFCLK Duty Cycle
30
70
%
REFCLK Rise Time (20%-80%)
2
ns
REFCLK Fall Time (20%-80%)
2
ns
Transmit Data or TXRST Set-up Time to
REFCLK (TXCKSEL
=
LOW)
Transmit Data or TXRST Hold Time from REFCLK
(TXCKSEL
=
LOW)
Receive Data Access Time from REFCLK (RXCKSEL
=
LOW)
Receive Data Valid Time from REFCLK
(RXCKSEL
=
LOW)
Receive Data Access Time from RXCLK (RXCKSEL
=
LOW)
Receive Data Valid Time from RXCLK
(RXCKSEL
=
LOW)
Receive Data Access Time from RXCLK (RXCKSEL
=
LOW)
Receive Data Valid Time from RXCLK
(RXCKSEL
=
LOW)
REFCLK Frequency Referenced to Received Clock Period
[24]
1.7
ns
0.8
ns
9.5
ns
4.0
ns
10UI
–
4.7
ns
1.0
ns
10UI
–
4.3
ns
0.2
ns
0.02
+0.02
%
CYP15G0101DXA Transmit Serial Outputs and TX PLL Characteristics
Over the Operating Range
Parameter
Description
Condition
Min.
Max.
Unit
t
B
t
RISE[17]
Bit Time
5000
660
ps
CML Output Rise Time 20%-80% (CML Test Load)
SPDSEL = HIGH
50
270
ps
SPDSEL = MID
100
500
ps
SPDSEL = LOW
200
1000
ps
t
FALL[17]
CML Output Fall Time 80%-20% (CML Test Load)
SPDSEL = HIGH
50
270
ps
SPDSEL = MID
100
500
ps
SPDSEL = LOW
200
1000
ps
t
DJ[17, 25, 27]
t
RJ[17, 26, 27]
t
TXLOCK
Deterministic Jitter (peak-peak)
0.2
1.5 Gbps
0.2
1.5 Gbps
TBD
UI
Random Jitter (
σ
)
TBD
ps
Transmit PLL Lock to REFCLK
TBD
TBD
ns
Notes:
23. The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLK duty
cycle cannot be as large as 30%-70%,
24. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
REFCLK must be within ±200 PPM (
±
0.02%) of the transmitter PLL reference (REFCLK) frequency, necessitating a ±100-PPM crystal.
25. While sending continuous K28.5s, outputs loaded to a balanced 100
load, measured at the crosspoint of the differential outputs over the operating range.
26. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the
operating range.
27. Total jitter is calculated at an assumed BER of 1E
12. Hence: Total Jitter (t
J
)
=
(t
RJ
* 14) + t
DJ
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線(xiàn)路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0101DXB-BBI | 功能描述:電信線(xiàn)路管理 IC Single Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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