參數(shù)資料
型號(hào)： CYP15G0101DXA-BBI
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Single Channel HOTLink II Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA100
封裝： 11 X 11 MM, 1.40 MM HEIGHT, BGA-100
文件頁(yè)數(shù)： 6/40頁(yè)
文件大小： 527K
代理商： CYP15G0101DXA-BBI
CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 6 of 40
SCSEL
LVTTL Input,
synchronous,
internal pull-down,
sampled by
TXCLK
↑
or REFCLK
↑
[1]
Special Character Select
. Used in some transmit modes along with TXCT[1:0] to en-
code special characters or to initiate a Word Sync Sequence.
Transmit Path Clock and Clock Control
TXCKSEL
3-Level Select
[2]
static control input
Transmit Clock Select
. Selects the clock source, used to write data into the Transmit
Input Register, of the transmit channel.
When LOW, the Input Register is clocked by REFCLK
↑
[1]
.
When HIGH or MID, TXCLK
↑
is the Input Register clock for TXD[7:0] and TXCT[1:0].
Transmit Clock Output
. This true and complement output clock is synthesized by the
transmit PLL and operates synchronous to the internal transmit character clock. It op-
erates at either the same frequency as REFCLK, or at twice the frequency of REFCLK
(as selected by TXRATE). TXCLKO
±
is always equal to the transmit VCO bit-clock
frequency
÷
10. This output clock has no direct phase relationship to REFCLK or the
recovered character clock.
Transmit PLL Clock Rate Select
. When TXRATE = HIGH, the Transmit PLL multiplies
REFCLK by 20 to generate the serial bit-rate clock. When TXRATE = LOW, the transmit
PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See
Table 9
for a list
of operating serial rates.
When REFCLK is selected to clock the receive parallel interface (RXCKSEL = LOW),
the TXRATE input also determines if the clocks on the RXCLK
±
and RXCLKC+ outputs
are full or half-rate. When TXRATE = HIGH, these output clocks are half-rate clocks and
follow the frequency and duty cycle of the REFCLK input. When TXRATE = LOW, these
output clocks are full-rate clocks and follow the frequency and duty cycle of the REFCLK
input.
Transmit Path Input Clock
. This clock must be frequency-coherent to TXCLKO
±
, but
may be offset in phase. The internal operating phase of the input clock (relative to
REFLCK or TXCLKO+) is adjusted when TXRST = LOW and locked when
TXRST = HIGH.
TXCLKO
±
LVTTL Output
TXRATE
LVTTL Input,
Static Control input,
internal pull-down
TXCLK
LVTTL Clock Input,
internal pull-down
Transmit Path Mode Control
TXMODE[1:0]
3-Level Select
[2]
static control inputs
Transmit Operating Mode
. These inputs are interpreted to select one of nine operating
modes of the transmit path. See
Table 3
for a list of operating modes.
Receive Path Data Signals
RXD[7:0]
LVTTL Output,
synchronous to the
RXCLK
↑
output or
REFCLK
↑
[1]
input
LVTTL Output,
synchronous to the
RXCLK
↑
output or
REFCLK
↑
[1]
input
Parallel Data Output
. These outputs change following the rising edge of the selected
receive interface clock.
RXST[2:0]
Parallel Status Output
. These outputs change following the rising edge of the selected
receive interface clock.
When the Decoder is bypassed (DECMODE = LOW), RXST[1:0] become the two low-
order bits of the 10-bit received character, while RXST[2] = HIGH indicates the pres-
ence of a Comma character in the Output Register.
When the Decoder is enabled (DECMODE = HIGH), RXST[1:0] provide status of the
received signal. See
Table 17
for a list of Receive Character status.
Note:
2.
3-Level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH.
The LOW level is usually implemented by direct connection to V
(ground). The HIGH level is usually implemented by direct connection to V
CC
(power). When
not connected or allowed to float, a 3-Level select input will self-bias to the MID level.
Pin Descriptions
(continued)
CYP15G0101DXA Single Channel HOTLink II
Transceiver
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料
PDF描述
CYP15G0402DX-BGC Quad HOTLinkII SERDES
CYP15G0402DX Quad HOTLinkII SERDES
CYP15G0402DX-BGI Quad HOTLinkII SERDES
CYP15G0402DXB Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器)
CYV15G0402DXB Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYP15G0101DXB 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver
CYP15G0101DXB_11 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards
CYP15G0101DXB_12 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver
CYP15G0101DXB-BBC 功能描述:電信線(xiàn)路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYP15G0101DXB-BBI 功能描述:電信線(xiàn)路管理 IC Single Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*