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參數(shù)資料
| 型號： | CYP15G0101DXA-BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Single Channel HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA100 |
| 封裝： | 11 X 11 MM, 1.40 MM HEIGHT, BGA-100 |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 527K |
| 代理商： | CYP15G0101DXA-BBI |
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CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 16 of 40
stream. In this mode the LFI output is HIGH (unless one of the
other status monitors indicates that the received signal is out
of specification). If the Range-Control Monitor indicates that
the received data stream signaling-rate is out of specification,
the phase detector is configured to track the local REFCLK
input, and the LFI output is asserted LOW.
The specific trip points for this compare function are listed in
Table 11
. Because the compare function operates with two
asynchronous clocks, there is a small uncertainty in the mea-
surement. The switch points are asymmetric to provide hyster-
esis to the operation.
Receive Channel Enabled
The CYP15G0101DXA receive channel can be enabled and
disabled through the BOE[0] input, as controlled by the RXLE
latch-enable signal. When RXLE = HIGH, the signal present
on the BOE[0] inputs is passed through the Receive Channel
Enable Latch to control the PLL and logic of the receive chan-
nel. The BOE[1:0] input functions are listed in
Table 8
.
When RXLE = HIGH and BOE[0] = HIGH, the receive channel
is enabled to receive and decode a serial stream from the Line
Receiver. When RXLE = HIGH and BOE[0] = LOW, the re-
ceive channel is disabled and internally configured for mini-
mum power dissipation. When disabled, the channel indicates
a constant LFI output. When RXLE returns LOW, the values
present on the BOE[1:0] inputs are latched in the Receive
Channel Enable Latch, and remain there until RXLE returns
HIGH to opened the latch again.
Note:
When a disabled receive channel is re-enabled, the
status of the LFI output and data on the parallel outputs may
be indeterminate for up to 10ms.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from a
received serial stream is performed by a Clock/Data Recovery
(CDR) block within the receive channel. The clock extraction
function is performed by a high-performance embedded
phase-locked loop (PLL) that tracks the frequency of the tran-
sitions in the incoming bit stream and aligns the phase of the
internal bit-rate clock to the transitions in the serial data
stream.
The CDR accepts a character-rate (bit-rate
÷
10) or half-char-
acter-rate (bit-rate
÷
20) reference clock from the REFCLK in-
put. This REFCLK input is used to ensure that the VCO (within
the CDR) is operating at the correct frequency (rather than
some harmonic of the bit-rate)
to reduce PLL acquisition time
and to limit unlocked frequency excursions of the CDR VCO
when there is no input data is present at the selected Serial
Line Receiver.
Regardless of the type of signal present, the CDR will attempt
to recover a data bit stream from it. If the frequency of the
recovered data stream is outside the limits set by the Range
Control Monitor, the CDR PLL will track REFCLK instead of the
data stream. When the frequency of the data stream returns
to a valid frequency, the CDR PLL is allowed to track the re-
ceived data stream. The frequency of REFCLK is required to
be within
±
200 ppm of the frequency of the clock that drives
the REFCLK input of the
remote
transmitter to ensure a lock
to the incoming data stream.
For systems using multiple or redundant connections, the LFI
output can be used to select an alternate data stream. When
an LFI indication is detected, external logic can toggle selec-
tion of the IN1± and IN2± inputs through the INSEL input.
When a port switch takes place, it is necessary for the receive
PLL to reacquire the new serial stream and frame to the incom-
ing character boundaries.
Deserializer/Framer
Each CDR circuit extracts bits from the serial data stream and
clocks these bits into the Shifter/Framer at the bit-clock rate.
When enabled, the Framer examines the data stream looking
for one or more Comma or K28.5 characters at all possible bit
positions. The location of these characters in the data stream
are used to determine the character boundaries of all following
characters.
Framing Character
The CYP15G0101DXA allows selection of either of two com-
binations of framing characters to support requirements of dif-
ferent interfaces. The selection of the framing character is
made through the FRAMCHAR input.
The specific bit combinations of these framing characters are
listed in
Table 12
. When the specific bit combination of the
selected framing character is detected by the Framer, the
boundaries of the characters present in the received data
stream are known.
Framer
The Framer operates in one of three different modes, as se-
lected by the RFMODE input. In addition, the Framer itself may
be enabled or disabled through the RFEN input. When
RFEN = LOW, the Framer is disabled, and no combination of
bits in a received data stream will alter the character bound-
Table 11. Receive Signaling Rate Range Control criteria
Current RX PLL
Tracking Source
Selected data
stream
Frequency
Difference
Between
Transmit Character
Clock & RX VCO
<1708 ppm
1708-1953 ppm
>1953 ppm
Next RX PLL
Tracking
Source
Data Stream
Indeterminate
REFCLK
(LFI = HIGH)
REFCLK
(LFI = LOW)
<488 ppm
488-732 ppm
>732 ppm
Data Stream
Indeterminate
REFCLK
Table 12. Framing Character Selector
FRAMCHAR
MID (Open)
Bits detected in Framer
Character Name
Comma+
Comma
K28.5
+
K28.5
Bits Detected
00111110XX
[7]
or 11000001XX
0011111010 or
1100000101
HIGH
Note:
7.
The standard definition of a Comma contains only seven bits. However,
since all valid Comma characters within the 8B/10B character set also
have the 8th bit as an inversion of the 7th bit, the compare pattern is
extended to a full eight bits to reduce the possibility of a framing error.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0101DXB-BBI | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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