MOTOROLA
8-4
INSTRUCTION TIMING
CPU16
REFERENCE MANUAL
8.2.2.4 Stack Manipulation Instructions
Aligned stack manipulation instructions comply with normal program access con-
straints, but have extra operand access cycles for stacking operations. Treat mis-
aligned stacking operations as byte transfers on a misaligned 16-bit bus.
Table 8-3
shows program and operand access cycles for each instruction.
*The last operand read from the stack is ignored
8.2.2.5 Stop and Wait Instructions
Stop and wait instructions have normal program access cycles, but differ from regular
instructions in number of operand accesses. If LPSTOP is executed at a time when
the CCR S bit is equal to zero, it must make one operand access to store the CCR IP
field. WAI performs one prefetch access to establish a PC value that insures proper
stacking and return from interrupt.
Table 8-4
shows program and operand access cycles for each instruction.
8.2.2.6 Move Instructions
Move instructions have normal program access cycles, but differ from regular instruc-
tions in number of operand accesses. Each move requires two operand accesses, one
to read the data from the source address and one to write it to the destination address.
Table 8-5
shows program and operand access cycles for each instruction.
Table 8-3 Stack Manipulation Timing
Instruction
Operand
Access
1
1
N
N + 1
6
Program
Access
1
1
1
1
1
Comment
PSHA/PSHB
PULA/PULB
PSHM
PULM
PSHMAC/PULMAC
Byte operation
Byte operation
N = Number of registers pushed
N = Number of registers pulled*
Stacks/retrieves all MAC registers
Table 8-4 Stop and Wait Timing
Instruction
Operand
Access
Program
Access
1
1
Comment
LPSTOP1
WAI
Operand access only when CCR S Bit = 0
—
0
Table 8-5 Move Timing
Instruction
Operand
Access
2
2
Program
Access
2
3
Comment
MOVB/MOVW
MOVB/MOVW
IXP to EXT, EXT to IXP addressing modes
EXT to EXT addressing mode
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.