MOTOROLA
6-274
INSTRUCTION GLOSSARY
CPU16
REFERENCE MANUAL
BRA
BRCLR
2
Branch Always
Branch if Bit(s) Clear
If 1 = 1, branch
If (M)
(Mask) = 0, branch
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
B0
CB
DB
EB
0A
rr
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IND16, Y
IND16, Z
EXT
1A
2A
3A
mm ff rr
mm ff rr
mm ff rr
mm gggg
rrrr
mm gggg
rrrr
mm gggg
rrrr
mm hh ll
rrrr
rr
mm ff rr
mm ff rr
mm ff rr
mm gggg
rrrr
mm gggg
rrrr
mm gggg
rrrr
mm hh ll
rrrr
mm ff
mm ff
mm ff
mm gggg
mm gggg
mm gggg
mm hh ll
gggg
mmmm
gggg
mmmm
gggg
mmmm
hh ll
mmmm
rr
10, 12
10, 12
10, 12
10, 14
10, 14
10, 14
10, 14
BRN
BRSET
2
Branch Never
Branch if Bit(s) Set
If 1 = 0, branch
If (M) (Mask) = 0, branch
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
B1
8B
9B
AB
0B
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IND16, Y
IND16, Z
EXT
1B
2B
3B
10, 12
10, 12
10, 12
10, 14
10, 14
10, 14
10, 14
BSET
Set Bit(s)
(M)
(Mask)
M
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
IND16, X
1709
1719
1729
09
19
29
39
2709
8
8
8
8
8
8
8
10
—
—
—
—
0
BSETW
Set Bit(s) in Word
(M : M + 1)
(Mask)
M : M + 1
IND16, Y
IND16, Z
EXT
2719
2729
2739
10
10
10
—
—
—
—
0
BSR
Branch to Subroutine
(PK : PC) - 2
PK : PC
Push (PC)
(SK : SP) - 2
SK : SP
Push (CCR)
(SK : SP) - 2
SK : SP
(PK : PC)
+
Offset
PK : PC
If V = 0, branch
REL8
36
10
—
—
—
—
—
—
—
—
BVC
2
Branch if Overflow
Clear
Branch if Overflow Set
REL8
B8
rr
6, 2
—
—
—
—
—
—
—
—
BVS
2
CBA
CLR
If V = 1, branch
REL8
B9
rr
6, 2
—
—
—
—
—
—
—
—
Compare A to B
Clear a Byte in
Memory
(A)
(B)
$00
M
INH
371B
05
15
25
1705
1715
1725
1735
3705
3715
27F5
2775
27B7
2705
2715
2725
2735
—
ff
ff
ff
2
4
4
4
6
6
6
6
2
2
2
2
2
6
6
6
6
—
—
—
—
—
—
—
—
0
1
0
0
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
EXT
INH
INH
INH
INH
INH
IND16, X
IND16, Y
IND16, Z
EXT
gggg
gggg
gggg
hh ll
—
—
—
—
—
gggg
gggg
gggg
hh ll
CLRA
CLRB
CLRD
CLRE
CLRM
CLRW
Clear A
Clear B
Clear D
Clear E
Clear AM
Clear a Word in
Memory
$00
A
$00
B
$0000
D
$0000
E
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
0
—
0
0
0
0
—
0
1
1
1
1
—
1
0
0
0
0
—
0
0
0
0
0
—
0
$000000000
AM[35:0]
$0000
M
:
M
+
1
Table 6-36 Instruction Set Summary (Continued)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
MV
H
EV
N
Z
V
C
F
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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.