CPU16
REFERENCE MANUAL
OVERVIEW
MOTOROLA
1-1
SECTION 1OVERVIEW
The CPU16 is a high-speed 16-bit central processing unit used in the M68HC16 family
of modular microcontrollers. The CPU16 uses a prefetch mechanism and a three-in-
struction pipeline to reduce instruction execution time. The CPU16 instruction set has
been optimized for high performance and high-level language support. Program diag-
nosis is enhanced by a background debugging mode.
The CPU16 has two 16-bit general-purpose accumulators and three 16-bit index reg-
isters. It supports 8-bit (byte), 16-bit (word), and 32-bit (long-word) load and store op-
erations, as well as 16-bit and 32-bit signed fractional operations.
CPU16 memory space includes a 1 Mbyte data space and a 1 Mbyte program space.
Twenty-bit addressing and transparent bank switching are used to implement extend-
ed memory. In addition, most instructions automatically handle bank boundaries.
The CPU16 provides M68HC11 users a migration path to higher performance. CPU16
architecture is a superset of M68HC11 CPU architecture — all M68HC11 CPU re-
sources are available in the CPU16. The CPU16 and M68HC11 CPU instruction sets
are source code compatible. M68HC11 CPU instructions are either directly imple-
mented in the CPU16 instruction set, or have been replaced by equivalent instructions.
The CPU16 includes instructions and hardware to implement control-oriented digital
signal processing functions with a minimum of interfacing. A multiply and accumulate
unit provides the capability to multiply signed 16-bit fractional numbers and store the
resulting 32-bit fixed point product in a 36-bit accumulator. Modulo addressing sup-
ports finite impulse response filters.
Documentation for the M68HC16 family follows the modular design concept. There is
a comprehensive user's manual for each device in the product line, and a detailed ref-
erence manual for each of the individual on-chip modules.
F
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