參數(shù)資料
型號(hào)： BX80546KG3600FA
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 3600 MHz, MICROPROCESSOR, CPGA604
封裝： FLIP CHIP, MICRO PGA-604
文件頁(yè)數(shù)： 54/106頁(yè)
文件大?。?/td> 4724K
代理商： BX80546KG3600FA
Datasheet
51
Signal Definitions
MCERR#
I/O
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable
error without a bus protocol violation. It may be driven by all processor front
side bus agents.
MCERR# assertion conditions are configurable at a system level.
Assertion options are defined by the following options:
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus transaction
after it observes an error.
Asserted by any bus agent when it observes an error in a bus
transaction.
For more details regarding machine check architecture, refer to the IA-32
Intel Architecture Software Developer’s Manual, Volume 3: System
Programming Guide.
Since multiple agents may drive this signal at the same time, MCERR# is a
wired-OR signal which must connect the appropriate pins of all processor
front side bus agents. In order to avoid wired-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, MCERR# is
activated on specific clock edges and sampled on specific clock edges.
ODTEN
I
ODTEN (On-die termination enable) should be connected to VTT to enable
on-die termination for end bus agents. For middle bus agents, pull this
signal down via a resistor to ground to disable on-die termination.
Whenever ODTEN is high, on-die termination will be active, regardless of
other states of the bus.
OPTIMIZED/
COMPAT#
I
This is an input pin to the processor to determine if the processor is in an
optimized platform or a compatible platform. This signal does includes a
weak on-die pull-up to VTT.
PROCHOT#
O
PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor die temperature
has reached its factory configured trip point. This indicates that the
processor Thermal Control Circuit (TCC) has been activated, if enabled.
See Section 6.2.4 for more details.
PWRGOOD
I
PWRGOOD (Power Good) is an input. The processor requires this signal
to be a clean indication that all processor clocks and power supplies are
stable and within their specifications. “Clean” implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the
time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must
again be stable before a subsequent rising edge of PWRGOOD. It must
also meet the minimum pulse width specification in Table 2-14, and be
followed by a 1-10 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should be
driven high throughout boundary scan operation.
3
REQ[4:0]#
I/O
REQ[4:0]# (Request Command) must connect the appropriate pins of all
processor front side bus agents. They are asserted by the current bus
owner to define the currently active transaction type. These signals are
source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal
description for details on parity checking of these signals.
4
Table 4-1. Signal Definitions (Sheet 7 of 10)
Name
Type
Description
Notes
相關(guān)PDF資料
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