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參數(shù)資料
| 型號： | BX80546KG3600FA |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 3600 MHz, MICROPROCESSOR, CPGA604 |
| 封裝： | FLIP CHIP, MICRO PGA-604 |
| 文件頁數(shù)： | 17/106頁 |
| 文件大小： | 4724K |
| 代理商： | BX80546KG3600FA |
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18
Datasheet
Electrical Specifications
2.2.3
Front Side Bus AGTL+ Decoupling
The 64-bit Intel Xeon processor with 2 MB L2 cache integrates signal termination on the die, as
well as part of the required high frequency decoupling capacitance on the processor package.
However, additional high frequency capacitance must be added to the baseboard to properly
decouple the return currents from the front side bus. Bulk decoupling must also be provided by the
baseboard for proper AGTL+ bus operation.
2.3
Front Side Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the
processor. As in previous processor generations, the 64-bit Intel Xeon processor with 2 MB L2
cache core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier
is set during manufacturing. The Platform Requirement Bit (PRB) is set for all 64-bit Intel Xeon
processors with 2 MB L2 cache and 64-bit Intel Xeon MV processors with 2 MB L2 cache, which
means the default setting will be the minimum speed for the processor. Software must override this
setting to permit operation at the designated processor frequency. The PRB will NOT be set for 64-
bit Intel Xeon LV processors with 2 MB L2 cache. As a result, these processors will begin
operation at their default maximum speed. It is possible to override this setting using software,
permitting operation at a speed lower than the processors’ tested frequency.
The BCLK[1:0] inputs directly control the operating speed of the front side bus interface. The
processor core frequency is configured during reset by using values stored internally during
manufacturing. The stored value sets the highest bus fraction at which the particular processor can
operate. If lower speeds are desired, the appropriate ratio can be configured by setting bits [15:8] of
the IA32_FLEX_BRVID_SEL MSR.
Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which
requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking. The
64-bit Intel Xeon processor with 2 MB L2 cache uses differential clocks. Table 2-1 contains core
frequency to front side bus multipliers and their corresponding core frequencies.
NOTE: Individual processors operate only at or below the frequency marked on the package.
2.3.1
Front Side Bus Frequency Select Signals (BSEL[1:0])
BSEL[1:0] are open-drain outputs, which must be pulled up to VTT, and are used to select the front
side bus frequency. Please refer to Table 2-11 for DC specifications. Table 2-2 defines the possible
combinations of the signals and the frequency associated with each combination. The frequency is
Table 2-1. Core Frequency to Front Side Bus Multiplier Configuration
Core Frequency to Front Side Bus Multiplier
Core Frequency with 200 MHz Front Side Bus Clock
1/14
2.80 GHz
1/15
3 GHz
1/16
3.20 GHz
1/17
3.40 GHz
1/18
3.60 GHz
1/19
3.80 GHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| BX80546PG3000E S L8JZ | 制造商:Intel 功能描述: |
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