參數(shù)資料
型號(hào)： BX80546KG3600FA
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 3600 MHz, MICROPROCESSOR, CPGA604
封裝： FLIP CHIP, MICRO PGA-604
文件頁(yè)數(shù)： 22/106頁(yè)
文件大?。?/td> 4724K
代理商： BX80546KG3600FA
22
Datasheet
Electrical Specifications
2.5
Reserved Or Unused Pins
All Reserved pins must remain unconnected. Connection of these pins to VCC, VTT, VSS, or to any
other signal (including each other) can result in component malfunction or incompatibility with
future processors. See Section 5 for a pin listing of the processor and the location of all Reserved
pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. In a system level design, on-die termination has been included by the processor to
allow end agents to be terminated within the processor silicon for most signals. In this context, end
agent refers to the bus agent that resides on either end of the daisy-chained front side bus interface
while a middle agent is any bus agent in between the two end agents. For end agents, most unused
AGTL+ inputs should be left as no connects as AGTL+ termination is provided on the processor
silicon. However, see Table 2-5 for details on AGTL+ signals that do not include on-die
termination. For middle agents, the on-die termination must be disabled, so the platform must
ensure that unused AGTL+ input signals which do not connect to end agents are connected to VTT
via a pull-up resistor. Unused active high inputs, should be connected through a resistor to ground
(VSS). Unused outputs can be left unconnected, however this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used
when tying bidirectional signals to power or ground. When tying any signal to power or ground, a
resistor will also allow for system testability. Resistor values should be within ± 20% of the
impedance of the baseboard trace for front side bus signals. For unused AGTL+ input or I/O
signals, use pull-up resistors of the same value as the on-die termination resistors (RTT).
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may
be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated
may interfere with some TAP functions, complicate debug probing, and prevent boundary scan
testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design
Guide (See Section 1.2).
All TESTHI[6:0] pins should be individually connected to VTT via a pull-up resistor which
matches the nominal trace impedance. TESTHI[3:0] and TESTHI[6:5] may be tied together and
pulled up to VTT with a single resistor if desired. However, utilization of boundary scan test will
not be functional if these pins are connected together. TESTHI4 must always be pulled up
independently from the other TESTHI pins. For optimum noise margin, all pull-up resistor values
used for TESTHI[6:0] pins should have a resistance value within ± 20 % of the impedance of the
board transmission line traces. For example, if the nominal trace impedance is 50
, then a value
between 40
and 60 should be used.
N/C (no connect) pins of the processor are not utilized by the processor. There is no connection
from the pin to the die. These pins may perform functions in future processors intended for
platforms using the 64-bit Intel Xeon processor with 2 MB L2 cache.
2.6
Front Side Bus Signal Groups
The front side bus signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF as a reference level. In this document, the term
“AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving.
Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group
when driving. AGTL+ asynchronous outputs can become active anytime and include an active
pMOS pull-up transistor to assist during the first clock of a low-to-high voltage transition.
相關(guān)PDF資料
PDF描述
BU-63925D0-301 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
BU-63925F0-300 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70
BU-63925G3-201 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
BU-64703B3-200 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80
BU-64703B8-192 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CBGA80
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BX80546KG3600FUS L8P3 制造商:Intel 功能描述:MPU XEON NETBURST 64BIT 90NM 3.6GHZ 604PIN FCMPGA4 - Boxed Product (Development Kits)
BX80546PE2800E 制造商:Intel 功能描述:P4 Socket 478 2.8GHzE 533MHz with fan
BX80546PG3000E S L7PM 制造商:Intel 功能描述:
BX80546PG3000E S L8JZ 制造商:Intel 功能描述:
BX80546PG3200E 制造商:Intel 功能描述:MPU PENTIUM 4 PROCESSOR NETBURST 90NM 3.2GHZ - Boxed Product (Development Kits)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*