參數(shù)資料
型號： BX80546KG3600FA
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 3600 MHz, MICROPROCESSOR, CPGA604
封裝： FLIP CHIP, MICRO PGA-604
文件頁數(shù)： 20/106頁
文件大?。?/td> 4724K
代理商： BX80546KG3600FA
20
Datasheet
Electrical Specifications
NOTES:
1. Diagram not to scale.
2. No specifications for frequencies beyond fcore (core frequency).
3. fpeak, if existent, should be less than 0.05 MHz.
4. fcore represents the maximum core frequency supported by the platform.
2.4
Voltage Identification (VID)
The Voltage Identification (VID) specification for the 64-bit Intel Xeon processor with 2 MB L2
cache is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 10.1 Design Guidelines. The voltage set by the VID signals is the maximum voltage
allowed by the processor (please see Section 2.11.2 for VCC overshoot specifications). VID signals
are open drain outputs, which must be pulled up to VTT. Please refer to Table 2-11 for the DC
specifications for these signals. A minimum voltage is provided in Table 2-8 and changes with
frequency. This allows processors running at a higher frequency to have a relaxed minimum
voltage specification. The specifications have been set such that one voltage regulator can operate
with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two devices at
the same core speed may have different default VID settings. This is reflected by the VID range
values provided in Table 2-8. Refer to the 64-bit Intel Xeon Processor with 800 MHz System
Bus (1 MB and 2 MB L2 Cache Versions) Specification Update for further details on specific valid
core frequency and VID values of the processor.
The processor uses six voltage identification signals, VID[5:0], to support automatic selection of
power supply voltages. Table 2-3 specifies the voltage level corresponding to the state of VID[5:0].
A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the
processor socket is empty (VID[5:0] = x11111), or the voltage regulation circuit cannot supply the
voltage that is requested, it must disable itself. See the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator-Down (EVRD) 10.1 Design Guidelines for further details.
The 64-bit Intel Xeon processor with 2 MB L2 cache provides the ability to operate while
transitioning to an adjacent VID and its associated processor core voltage (VCC). This will
represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage
state change may result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 2-8 includes VID step sizes and DC
shift ranges. Minimum and maximum voltages must be maintained as shown in Table 2-9 and
The VRM or VRD used must be capable of regulating its output to the value defined by the new
VID. DC specifications for dynamic VID transitions are included in Table 2-8 and Table 2-9.
Please refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 10.1 Design Guidelines for further details.
Power source characteristics must be guaranteed to be stable whenever the supply to the voltage
regulator is stable.
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