參數(shù)資料
型號: AX88780_07
廠商: ASIX Electronics Corporation
英文描述: IC,D/A CONVERTER,MC144110DW, 6-BIT,5-15V,SOIC-20,3-7US SER.
中文描述: 高性能非PCI單芯片32位10/100M自適應(yīng)快速以太網(wǎng)控制器
文件頁數(shù): 35/55頁
文件大小: 379K
代理商: AX88780_07
AX88780
35
ASIX ELECTRONICS CORPORATION
1=Full-duplex operation
0= Normal operation
Collision test:
1=Enable collision test
0= Normal operation
Reserved
7
COLTST
R/W
0
6:0
-
R
X
5.2 BMSR--Basic Mode Status Register
Index = 0x01
Field Name
Type
15
100BCAP
R
Default
0, PS
Description
100Base-T4 capability
0 = AX88780 is not able to execute 100 BASE-T4 mode.
100BASE-TX full-duplex capability:
1= AX88780 is able to perform in 100BASE-TX full-duplex mode.
100BASE-TX half-duplex capability:
1 = AX88780 is able to perform in 100BASE-TX half-duplex mode.
10BASE-T full-duplex capability:
1 = AX88780 is able to perform in 10BASE-T full-duplex mode.
10BASE-T half-duplex capability:
1 = AX88780 is able to perform in 10BASE-T half-duplex mode.
Reserved, default 4’b0000
Management frame preamble suppression:
0 = AX88780 will not accept management frames with preamble suppressed.
Auto negotiation completion:
1 = auto-negotiation process is complete.
0 = auto-negotiation process is not completed
Remote fault status:
1 = The link partner signals a far-end fault, read to clear.
0 = Remote fault condition is not detected
Auto configuration ability:
1 = AX88780 is able to perform auto-negotiation
Link status:
1= Valid link is established, (100Mb/s or 10Mb/s operation)
0= Valid link is not established
Jabber detection:
1= Jabber condition is detected.
0 = Jabber condition is not detected
Extended capability:
1= Extended register capable
0= Basic register capability only.
14
100BFUL
R
1, PS
13
100BHAF
R
1, PS
12
10BFUL
R
1, PS
11
10BHAF
R
1, PS
10:7
6
-
R
R
All 0’s
0, PS
MFPS
5
AUTONEST R
0
4
RFST
RC
0, LH
3
AUTOCFG R
1, PS
2
LNKST
R
0, LL
1
JABDET
R
0, LH
0
EXTCAP
R
1, PS
5.3 PHYIDR0--PHY Identifier 0 Register
Index = 0x02
Field Name
Type
15:0
OUIMSB R
Default
0x003B
PS
Description
OUI most significant bits.
Bits 3 to 18 of the OUI are mapped to bits 15 to 0 of this register respectively. The
most significant two bits of the OUI are ignored
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