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參數(shù)資料
| 型號： | AX88780_07 |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | IC,D/A CONVERTER,MC144110DW, 6-BIT,5-15V,SOIC-20,3-7US SER. |
| 中文描述： | 高性能非PCI單芯片32位10/100M自適應(yīng)快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 10/55頁 |
| 文件大?。?/td> | 379K |
| 代理商： | AX88780_07 |
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AX88780
10
ASIX ELECTRONICS CORPORATION
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
WEN
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
I3
124
122
121
120
118
116
114
113
112
111
110
109
108
42
41
34
33
32
31
30
29
28
26
25
24
23
22
21
44
Data bus bit19, internal pull down.
*
Data bus bit20, internal pull down.
*
Data bus bit21, internal pull down.
*
Data bus bit22, internal pull down.
*
Data bus bit23, internal pull down.
*
Data bus bit24, internal pull down.
*
Data bus bit25, internal pull down.
*
Data bus bit26, internal pull down.
*
Data bus bit27, internal pull down.
*
Data bus bit28, internal pull down.
*
Data bus bit29, internal pull down.
*
Data bus bit30, internal pull down.
*
Data bus bit31, internal pull down.
*
Address bus bit1.
Address bus bit2.
Address bus bit3.
Address bus bit4.
Address bus bit5.
Address bus bit6.
Address bus bit7.
Address bus bit8.
Address bus bit9.
Address bus bit10.
Address bus bit11.
Address bus bit12.
Address bus bit13.
Address bus bit14.
Address bus bit15.
Data Write Enable
Host drives WEN and it is active low.
Chip Select Enable
Host drives CSN and it is active low.
Data Output Enable
Host drives OEN and it is active low.
CSN
I3
45
OEN
I3
43
*Note: The internal Pull-down of HD16 to HD31 will be disabled in 32-bit mode.
2.3 EEPROM Interface
Table 2: EEPROM Interface signals group
Pin NO
47
A low speed clock to EEPROM
48
Chip select to EEPROM device. This pin will be treated as full-duplex indicator
when bit10 of PHY_CTRL register is set to high. It is active high in full-duplex
mode, and low in half-duplex mode.
49
Data to EEPROM, valid in EECS is high and EECLK in rising edge.
This pin will be treated as collision indicator when bit10 of PHY_CTRL register is
set to high. It is active high in collision indicator.
50
Data from EEPROM
Pin Name
EECLK
EECS
Type
O3, 12mA
O3, 12mA
Pin Description
EEDI
O3, 12mA
EEDO
I3, PD
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AX88782 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88783 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88790L | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller |
| AX88796 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-in-1 Local Bus Fast Ethernet Controller |
| AX88796ALF | 制造商:ASIX 功能描述:10/100 MAC,COMMERCIAL 128PIN |
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