參數(shù)資料
型號： AX88780_07
廠商： ASIX Electronics Corporation
英文描述： IC,D/A CONVERTER,MC144110DW, 6-BIT,5-15V,SOIC-20,3-7US SER.
中文描述： 高性能非PCI單芯片32位10/100M自適應快速以太網(wǎng)控制器
文件頁數(shù)： 13/55頁
文件大小： 379K
代理商： AX88780_07
AX88780
13
ASIX ELECTRONICS CORPORATION
3.0 Functional Description
3.1 Host Interface
AX88780 supports a very simple SRAM-like interface. There are only 3 control signals to operate the read or write.
For write operation, host activates CSN and WEN to low with address and data bus. AX88780 will decode and latched the
data into internal buffer. For normal operation, the WEN needs at least 4 clocks duration for one 32/16-bit write operation.
The CSN can always be driven, but WEN must at least be de-asserted 1 clock before next access. For read operation, host
asserts CSN and OEN at least 5 clocks to AX88780, the data will be valid after 4 clocks. AX88780 also support burst mode
if host reads/writes AX88780 by continuous access. Note: The burst mode only supports in TX/RX, not supports in register
read/write. That is, read RX area from XXXX_0000 to XXXX_7FFF or write TX area from XXXX_8000 to XXXX_FBFF
can be accessed by burst mechanism.
3.2 System Address Range
AX88780 is suitable to attach to SRAM controller, so it needs 64K memory space to operate. The designer can
allocate any block (64K) in system space. From offset 0x0000 to 0x7FFF is for RX operation, and offset 0x8000 to
0xFBFF is for TX operation. The internal configuration register of AX88780 is allocated in offset 0xFC00 to 0xFCFF.
Below is the mapping of addressing.
Figure 3: 32-bit mode address mapping
3.3 TX Buffer Operation
AX88780 employs 4 descriptors to maintain transmit information, such as packet length, start bit. These descriptors
are located in offset 0xFC20, 0xFC24, 0xFC28 and 0xFC2C. Driver can choose any descriptor whenever there is data need
to be transmitted. Since there are only 4 descriptors, upon running out of descriptors, driver must wait for the descriptor is
to be released by AX88780.
3.4 RX Buffer Operation
AX88780 is built a 32K SRAM for RX operation. It utilizes ring structure to maintain the input data from PHY and
read out to host. There are two pointer registers located in offset 0xFC34 and 0xFC38. AX88780 will maintain RXCURT
register. Upon it receives a valid packet from PHY it will update RXCURT according to the packet length. Driver reads
data from AX88780 and maintains the RXBOUND register. When driver finishes reading packet, it must update
RXBOUND according to the packet length. AX88780 utilizes RXCURT and RXBOUND to provide receive buffer status,
full or empty.
R X a r e a
3 2 7 6 8 b y t e s
X X X X _ 0 0 0 0 h
X X X X _ 8 0 0 0 h
X X X X _ F C 0 0 h
3 1
0
T X a r e a
3 1 7 4 4 b y t e s
R e g i s t e r s a r e a
2 5 6 b y t e s
X X X X _ F D 0 0 h
N o u s e d a r e a
7 6 8 b y t e s
X X X X _ F F F F h
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