- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375384 > AX88780_07 (ASIX Electronics Corporation) IC,D/A CONVERTER,MC144110DW, 6-BIT,5-15V,SOIC-20,3-7US SER. PDF資料下載
參數(shù)資料
| 型號： | AX88780_07 |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | IC,D/A CONVERTER,MC144110DW, 6-BIT,5-15V,SOIC-20,3-7US SER. |
| 中文描述： | 高性能非PCI單芯片32位10/100M自適應快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 24/55頁 |
| 文件大小： | 379K |
| 代理商： | AX88780_07 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
AX88780
24
ASIX ELECTRONICS CORPORATION
4.14 RXBOUND--RX Boundary Pointer Register
Offset Address = 0xFC38 Default = 0x0000_07FF
Field
Name
Type
Default
31:11
-
R
All 0’s
10:0
RXBUNPTR
R/W
0x7FF
Description
Reserved
RX Line Boundary Pointer.
Point to the last line that has been read by driver. The unit of line is 16
bytes.
When driver finished reading packet from RX buffer, it must update this
field.
4.15 MAC_CFG0--MAC Configuration0 Register
Offset Address = 0xFC40 Default = 0x0000_8157
Field
Name
Type
Default
31:16
-
R
All 0’s
15
SPEED100
R/W
1
Description
Reserved
Line Speed Mode
When this bit is enabled, The MAC of AX88780 will operate in 100M
speed, otherwise it will operate in 10M speed. The line speed must
co-operate with setting of PHY.
1 = 100M
0 = 10M
Reserved, this bit must set to 0 for normal operation
Reserved, this bit must set to 0 for normal operation.
RX Flow Control
If this bit and bit8 of RX_CFG are enabled, MAC will perform flow
control and send pause on/off frame when the available space of receive
buffer is less than the value of RXBTHD0.
1 = enable
0 = disable
Reserved, this bit must set to 0 for normal operation.
Inter Packet Gap time: (IPG)
This field defines the back-to-back transmit packet gap for 10/100M only.
Reserved, keep the default value for normal operation.
14
13
12
-
-
R/W
R/W
R/W
0
0
0
RXFLOW
11
10:4
-
R/W 0
R/W
IPGT
0x15
3:0
-
R/W
0x7
4.16 MAC_CFG1--MAC Configuration1 Register
Offset Address = 0xFC44 Default = 0x0000_6000
Field
Name
Type
Default
31:15
-
R
All 0’s
14
PUSRULE
R/W
1
Description
Reserved
Pause Frame Check Rule
When this bit is set, AX88780 accepts pause frame that DA can be any
value.
1 = don’t check DA field.
0 = check DA is equal to “01 80 C2 00 00 01”
Check CRC of received Packet.
When this bit is enabled, AX88780 will drop any CRC error packet.
1 = enable
0 = disable
Reserved, keep all bits in ‘0’ for normal operation.
Duplex Mode.
1 = Full-Duplex mode
0 = Half-Duplex mode
TX Flow Enable
When this bit is enabled, MAC will block the transmitted operation when it
captures pause frame from Ethernet. The re-transmission will be activated
13
CRCCHK
R/W
1
12:7
6
-
R/W
R/W 0
All 0’s
DUPLEX
5
TXFLW_EN
R/W
0
相關PDF資料 |
PDF描述 |
|---|---|
| AX88780 | High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller |
| AX88790L | 10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller |
| AX88796BLF | IC,MC14411P |
| AX88796BLI | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller |
| AX88872P | 10/100BASE Dual Speed “Swipeater” Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AX88782 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88783 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88790L | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller |
| AX88796 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-in-1 Local Bus Fast Ethernet Controller |
| AX88796ALF | 制造商:ASIX 功能描述:10/100 MAC,COMMERCIAL 128PIN |
發(fā)布緊急采購，3分鐘左右您將得到回復。