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參數(shù)資料
| 型號： | AX88780_07 |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | IC,D/A CONVERTER,MC144110DW, 6-BIT,5-15V,SOIC-20,3-7US SER. |
| 中文描述： | 高性能非PCI單芯片32位10/100M自適應(yīng)快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 18/55頁 |
| 文件大?。?/td> | 379K |
| 代理商： | AX88780_07 |
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AX88780
18
ASIX ELECTRONICS CORPORATION
4.1 CMD--Command Register
Offset Address = 0xFC00 Default = 0x0000_0201
Field
Name
Type Default
31:16
-
R/W
All 0’s
15
RXVLAN
R/W
0
Description
Reserved
RX VLAN indicator
Driver enables this bit to indicate AX88780 that the received packet will
include 4 bytes VLAN tag; AX88780 will skip 4 bytes when it calculates the
checksum of IP, TCP or UDP packet.
1 = enable
0 = disable
TX VLAN indicator
Driver enables this bit to indicate AX88780 that the transmitted packet will
include 4 bytes VLAN tag; AX88780 will skip 4 bytes when it calculates the
checksum of IP, TCP or UDP packet.
1 = enable
0 = disable
Reserved
RX Function Enable
When this bit is enabled, MAC starts to receive packets.
1 = enable
0 = disable
TX Function Enable
When this bit is enabled, MAC could start to transmit packet to Ethernet.
1 = enable
0 = disable
Reserved
Interrupt Active Mode
Driver sets this bit to indicate AX88780 that the interrupt of system is
activated high or low.
1: Active high
0: Active low
Reserved
WAKEUP pin polarity
Driver sets this bit to indicate AX88780 that the polarity of system wake-up
signal is activated high or low.
1: Active high
0: Active low
14
TXVLAN
R/W
0
13:10
9
-
R/W
R/W
All 0’s
1
RXEN
8
TXEN
R/W
0
7
6
-
R/W
R/W
0
0
INTMOD
5:1
0
-
R/W
R/W
All 0’s
1
WAKEMOD
4.2 IMR--Interrupt Mask Register
Offset Address = 0xFC04 Default = 0x0000_0000
Field
Name
Type
Default
31:6
-
R
All 0’s
5
PHYMASK
R/W
0
Description
Reserved
PHY interrupt Mask
When this bit is enabled, an interrupt request from PHY set in bit 5 of
Interrupt Status Register will make AX88780 to issue an interrupt to host.
1 = enable
0 = disable
Packet Received Interrupt Mask
When this bit is enabled, a received interrupt request set in bit 4 of Interrupt
Status Register will make AX88780 to issue an interrupt to host.
1 = enable
0 = disable
Packet Transmitted Interrupt Mask
When this bit is enabled, a transmitted interrupt request set in bit 3 of Interrupt
Status Register will make AX88780 issue an interrupt to host.
4
PRIM
R/W
0
3
PTIM
R/W
0
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PDF描述 |
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| AX88780 | High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88782 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88783 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88790L | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller |
| AX88796 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-in-1 Local Bus Fast Ethernet Controller |
| AX88796ALF | 制造商:ASIX 功能描述:10/100 MAC,COMMERCIAL 128PIN |
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