參數(shù)資料
型號(hào)： AX88780_07
廠商： ASIX Electronics Corporation
英文描述： IC,D/A CONVERTER,MC144110DW, 6-BIT,5-15V,SOIC-20,3-7US SER.
中文描述： 高性能非PCI單芯片32位10/100M自適應(yīng)快速以太網(wǎng)控制器
文件頁數(shù)： 26/55頁
文件大?。?/td> 379K
代理商： AX88780_07
AX88780
26
ASIX ELECTRONICS CORPORATION
4.21 RXBTHD1--RX Buffer Threshold1 Register
Offset Address= 0xFC5C Default = 0x0000_0600
Field
Name
Type
Default
31:11
-
R
All 0’s
10:0
RXHIGHB
R/W
0x600
Description
Reserved
RX Remainder Capacity Upper-Bound
This field defines as upper bound of remainder size of RX buffer for pause
operation. If the flow control is enabled, MAC will stop to send pause
frame until the available space of receive buffer is more than this value.
The unit is 16-byte.
4.22 RXFULTHD--RX Buffer Full Threshold Register
Offset Address= 0xFC60 Default = 0x0000_0100
Field
Name
Type
Default
31:11
-
R
All 0’s
10:0
RXFULB
R/W
0x100
Description
Reserved
RX Full Threshold
This field defines the least capacity of RX buffer. AX88780 will cause RX
full if it remains capacity less than this value. The unit is 16-byte.
4.23 MISC—Misc. Control Register
Offset Address= 0xFC68 Default = 0x0000_0013
Field
Name
Type
Default
31:6
-
R
All 0’s
5
WAKE_LNK
R/W
0
Description
Reserved
WAKE-UP by Link-Up Function
If this bit is enabled, MAC will drive wakeup pin whenever there is link-up
occurrence. The polarity of wakeup pin is according to bit0 of CMD
register.
1= enable
0= disable
WAKE-UP by Magic Packet
If this bit is enabled, MAC will drive wakeup pin whenever there is magic
packet detected by hardware. The polarity of wakeup pin is according to
bit0 of CMD register.
1= enable wake-up by magic packet
0 = disable
Reserved
Software Reset Internal PHY
Driver set this bit to ‘0’ to reset internal PHY. The reset duration is
depended on whenever this bit is de-asserted by deriver.
1 = in normal operation
0 = in reset status
Software Reset MAC
Driver set this bit to ‘0’ to reset MAC. The reset duration is depended on
whenever this bit is de-asserted by deriver. After power-on, driver must
activate software reset MAC once before initial other registers.
1 = in normal operation
0 = in reset status
4
WAKE_MAG
R/W
1
3:2
1
-
SRST_PHY
R/W
R/W
00
1
0
SRST_MAC
R/W
1
相關(guān)PDF資料
PDF描述
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