參數(shù)資料
型號(hào)： AX88780_07
廠商： ASIX Electronics Corporation
英文描述： IC,D/A CONVERTER,MC144110DW, 6-BIT,5-15V,SOIC-20,3-7US SER.
中文描述： 高性能非PCI單芯片32位10/100M自適應(yīng)快速以太網(wǎng)控制器
文件頁(yè)數(shù)： 34/55頁(yè)
文件大小： 379K
代理商： AX88780_07
AX88780
34
ASIX ELECTRONICS CORPORATION
5.0 PHY Register
AX88780 is built a high performance 10/100M PHY for cost-effective. Driver can access these registers of PHY by
in-directed mechanism. For write operation, software firstly sets data to MDIODP register, then sets index and write enable
bit to MDIOCTRL register. AX88780 will access PHY by internal interface and clear the write enable bit whenever the
operation finished. For read operation, driver sets the index and read enable bit to MDIOCTRL register, then polls the
read-enable bit. The returned data will be put in MDIODP register whenever the read-enable bit is cleared.
Table 9 : PHY Register Mapping
Index
Name
Description
0x00
BMCR
Basic Mode Control Register
0x01
BMSR
Basic Mode Status Register
0x02
PHYIDR0
PHY Identifier 0 Register
0x03
PHYIDR1
PHY Identifier 1 Register
0x04
ANAR
Auto-negotiation Advertisement Register
0x05
ANLPAR
Auto-negotiation Link Partner Ability Register
0x06
ANER
Auto-negotiation Expansion Register
T
he following abbreviations apply to below sections for detained register description.
Access type
R = read only
RW= read/write
Attribute:
LL = latch low
LH = latch high
SC = Self-clearing
PS = Value is permanently set
X = don’t care
5.1 BMCR--Basic Mode Control Register
Index = 0x00
Field
15
Name
PHYRST
Type
R/W
Default
0, SC
Description
Soft reset:
1 = software reset PHY, this bit will be cleared when reset finish.
0 = normal operation
Loop back operation:
1 = Loop back enable
0 = Loop back disable
Speed selection:
1 = 100Mb/s
0 = 10Mb/s
Auto-negotiation enable:
1 = enable, bit8 and bit13 will be ignored when this bit is enabled.
0 = disable, bit8 and bit13 of this register determine the link speed and
mode.
Power down:
1 = power-down enable
0 = normal operation
Reserved
Auto-negotiation restart:
1=Restart auto-negotiation, this bit will be cleared when finish negotiation.
0=normal operation
Duplex mode:
14
LOOPBACK
R/W
0
13
SPDSEL
R/W
1
12
AUTONEG_EN RW
1
11
PHYPWDN
R/W
0
10
9
-
AUTONEG_RS R/W
R
0
0
8
DPLX
R/W
1
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