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參數資料
| 型號： | AX88780_07 |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | IC,D/A CONVERTER,MC144110DW, 6-BIT,5-15V,SOIC-20,3-7US SER. |
| 中文描述： | 高性能非PCI單芯片32位10/100M自適應快速以太網控制器 |
| 文件頁數： | 25/55頁 |
| 文件大?。?/td> | 379K |
| 代理商： | AX88780_07 |
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AX88780
25
ASIX ELECTRONICS CORPORATION
until the waiting time is expired.
1 = enable
0 = disable
Reserved, must set to ‘0s’ for normal operation
Reserved, must set to ‘0s’ for normal operation
4:1
0
-
-
R/W
R/W
0000
0
4.17 MAC_CFG2--MAC Configuration2 Register
Offset Address = 0xFC48 Default = 0x0000_0100
Field
Name
Type Default
15:8
-
R/W
0x01
7:2
JamLT
R/W
000000
Description
Reserved, keep this field in default value for normal operation.
Define Jam Limit for backpressure collision account.
Normally set this field at 0x19. It can avoid HUB port going to partition state due to
too many collisions. AX88780 will skip one frame collision backpressure when
collision counter equal to JamLT. The collision count will be reset to zero when
every transmit frame with no collision or receive a frame with no backpressure
collision.
Reserved, must set to ‘00’ for normal operation
1:0
-
R/W
00
4.18 MAC_CFG3--MAC Configuration3 Register
Offset Address = 0xFC4C Default = 0x0000_060E
Field
Name
Type
Default
15
NOABORT
R/W
0
Description
No Abort
When this bit is enabled, MAC will keep retry transmit current frame even
excessive collision otherwise it will abort current transmission due to
excessive collision.
1 = enable
0 = disable
Inter-Frame Gap segment1
Inter-Frame Gap segment2
13:7
6:0
IPGR1
IPGR2
R/W
R/W
0001100
0001110
4.19 TXPAUT--TX Pause Time Register
Offset Address= 0xFC54 Default = 0x001F_E000
Field
Name
Type
Default
31:23
-
R
22:0
TXPVAL R/W
0x1F_E000
Description
Reserved
TX Pause Time out
It is used to re-transmit a pause-on frame when pause timer expired and
receive buffer still not enough.
In 32-bit mode, this field should be set to 0x7F_8000.
In 16-bit mode, this field should be set to 0xFFFF at 10/100Mbps modes.
(Note: The bit 16 ~ 22 of this field are invalid in 16-bit mode.)
4.20 RXBTHD0--RX buffer Threshold0 Register
Offset Address= 0xFC58 Default = 0x0000_0300
Field
Name
Type
Default
31:11
-
R
All 0’s
10:0
RXLOWB R/W
0x300
Description
Reserved
RX Remainder Capacity Low-Bound
This field defines as the remainder capacity of RX buffer for pause
operation. If the flow control (bit12 of MACCFG0) is enabled, MAC will
send pause frame when the available space of receive buffer is less than
this value. The unit is 16-byte.
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