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參數資料
| 型號： | AT_8032 |
| 廠商： | Atmel Corp. |
| 英文描述： | 8-bit Embedded Microcontroller Core(8位嵌入式基于工業(yè)標準軟件兼容的微控制器) |
| 中文描述： | 8位嵌入式微控制器核心（8位嵌入式基于工業(yè)標準軟件兼容的微控制器） |
| 文件頁數： | 8/39頁 |
| 文件大?。?/td> | 532K |
| 代理商： | AT_8032 |
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AT_8032 Core
8
Reset
A reset is accomplished by holding the RST pin high for at
least two machine cycles (24 oscillator periods) while the
oscillator is running. The AT_8032 responds by generating
an internal reset.
The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2 of
every machine cycle. The port pins maintain their current
activities for 19 oscillator periods after a logic 1 has been
sampled at the RST pin, that is, for 19 to 31 oscillator peri-
ods after the external reset signal has been applied to the
RST pin.
While the RST pin is high, ALE and PSEN are weakly
pulled high. After RST is pulled low, it will take 1 to 2
machine cycles for ALE and PSEN to start clocking. For
this reason, other devices cannot be synchronized to the
internal timings of the AT_8032.
Driving the ALE and PSEN pins to 0 while the reset is
active could cause the AT_8032 to go into an indeterminate
state.
The internal reset algorithm writes 0s to all the SFRs
except the port latches, the Stack Pointer, and SBUF. The
port latches are initialized to FFH, the Stack Pointer to 07H,
and SBUF is indeterminate. Table 1 shows the SFRs and
their reset values. The internal RAM is not affected by the
reset. On power up the RAM content is indeterminate.
Table 1.
Reset Values of the SFRs
SFR Name
Reset Value
PC
0000H
ACC
00H
B
00H
PSW
00H
SP
07H
DPTR
0000H
P0-P3
FFH
IP
XX000000B
IE
0X000000B
TMOD
00H
TCON
00H
T2CON
00H
TH0
00H
TL0
00H
TH1
00H
TL1
00H
TH2
00H
TL2
00H
RCAP2H
00H
RCAP2L
00H
SCON
00H
SBUF
Indeterminate
PCON
HMOS 0XXXXXXXB
CHMOS 0XXX0000B
Table 1.
Reset Values of the SFRs (Continued)
SFR Name
Reset Value
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