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參數(shù)資料
| 型號： | AT_8032 |
| 廠商： | Atmel Corp. |
| 英文描述： | 8-bit Embedded Microcontroller Core(8位嵌入式基于工業(yè)標(biāo)準(zhǔn)軟件兼容的微控制器) |
| 中文描述： | 8位嵌入式微控制器核心（8位嵌入式基于工業(yè)標(biāo)準(zhǔn)軟件兼容的微控制器） |
| 文件頁數(shù)： | 26/39頁 |
| 文件大?。?/td> | 532K |
| 代理商： | AT_8032 |
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AT_8032 Core
26
requested. Transmission actually starts at S1P1 of the
machine cycle following the next rollover in the divide-by-
16 counter (thus, the bit times are synchronized to the
divide-by-16 counter, not to the
“
write to SBUF
”
signal).
The transmission begins with an activation of SEND, which
puts the start bit in TXD. One bit later, DATA is activated,
which connects the output bit of the transmit shift register to
TXD. The first shift pulse occurs one bit time after that.
As data bits shift out to the right, zeros are clocked in from
the left. When the MSB of the data byte is at the output
position of the shift register, then the 1 that was initially
loaded into the 9th position is just to the left of the MSB,
and all positions to the left of that contain zeroes. This con-
dition flags the TX Control unit to do one last shift and then
deactivate SEND and set TI. This occurs at the 10th divide-
by-16 rollover after
“
write to SBUF
”
.
Reception
Reception is initiated by a 1-to-0 transition detected at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immedi-
ately reset, and 1FFH is written into the input shift register.
Resetting the divide-by-16 counter aligns its rollover with
the boundaries of the incoming bit times.
The 16 states of the counter divide each bit period into
16ths. At the 7th, 8th and 9th counter states of each bit
period, the bit detector samples the value of RXD. The
value accepted is the value that was seen in at least 2 of
the 3 samples. This is done for noise rejection. If the value
accepted during the first bit time is not 0, the receiver is
reset and the unit goes back to looking for another 1-to-0
transition. This is to provide rejection of false start bits. If
the start bit proves valid, it is shifted into the input shift reg-
ister, and reception of the rest of the frame proceeds.
As data bits come in from the right, ones shift out to the left.
When the start bit arrives at the far left position in the shift
register (which in mode 1 is a 9-bit register), it flags the RX
Control block to do one last shift, load SBUF and RB8, and
set RI. The signal to load SBUF and RB8, and to set RI, will
be generated if, and only if, the following conditions are met
at the time as the final shift pulse is generated:
1.
RI = 0, and
2.
SM2 = 0, or the receive stop bit = 1
If neither of these two conditions is met, the received frame
is irretrievably lost. If both conditions are met, the stop bit
goes into RB8, the 8 data bits go into SBUF, and RI is acti-
vated. At this time, whether the above conditions are met or
not, the unit starts looking for a 1-to-0 transition at the RXD
input.
Operation in Modes 2 and 3
Eleven bits are transmitted (through TXD), or received
(through RXD): a start bit (0), 8 data bits (LSB first), a pro-
grammable 9th data bit, and a stop bit (1). On transmit the
9th data bit (TB8) can be assigned the value of 0 or 1. On
receive, the 9th data bit goes into RB8 in SCON. The baud
rate is programmable to either 1/32 or 1/64 of the oscillator
frequency in Mode 2. Mode 3 may have variable baud rate
generated from either Timer 1 or depending on the state of
TCLK and RCLK.
Transmission
Transmission is initiated by any instructions that use SBUF
as a destination register. The
“
write to SBUF
”
signal also
loads TB8 into the 9th bit position of the transmit shift regis-
ter and flags the TX Control unit that a transmission is
requested. Transmission commences at S1P1 of the
machine cycle following the next rollover in the divide-by-
16 counter (thus, the bit times are synchronized too the
divide-by-16 counter, not to the
“
write to SBUF
”
signal).
The transmission begins with an activation of SEND, which
puts the start bit in TXD. One bit time later, DATA is acti-
vated, which connects the output bit of the transmit shift
register to TXD. The first shift pulse occurs one bit time
after that. The first shift clocks a 1 (the stop bit) into the 9th
bit position of the shift register. Thereafter, only zeroes are
clocked in from the left. When TB8 is at the output position
of the shift register, then the stop bit is just to the left of
TB8, and all positions to the left of that contain zeroes. This
condition flags the TX Control unit to do one last shift and
then de-activate SEND and set TI. This occurs at the 11th
divide-by-16 rollover after
“
write to SBUF
”
.
Reception
Reception is initiated by a 1-to-0 transition detected at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immedi-
ately reset, and 1FFH is written to the input shift register.
At the 7th, 8th and 9th counter states of each bit period, the
bit detector samples the value of RXD. The accepted value
is the one that is seen in at least 2 of the 3 samples. If the
value accepted during the first bit time is not 0, the receive
circuits are reset and the unit goes back to looking for
another 1-to-0 transition. If the start bit proves valid, it is
shifted into the input shift register, and reception of the rest
of the frame proceeds.
As data bits come in from the right, ones shift out to the left.
When the start bit arrives at the far left position in the shift
register (which in Modes 2 and 3 is a 9-bit register), it flags
the RX Control block to do one last shift load SBUF and
RB8, and set RI. The signal to load SBUF and RB8, and to
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