參數(shù)資料
型號(hào)： AT_8032
廠商： Atmel Corp.
英文描述： 8-bit Embedded Microcontroller Core(8位嵌入式基于工業(yè)標(biāo)準(zhǔn)軟件兼容的微控制器)
中文描述： 8位嵌入式微控制器核心（8位嵌入式基于工業(yè)標(biāo)準(zhǔn)軟件兼容的微控制器）
文件頁(yè)數(shù)： 28/39頁(yè)
文件大小： 532K
代理商： AT_8032
AT_8032 Core
28
If an interrupt of higher-priority level goes active prior to
S5P2 of the machine cycle C3, it will be vectored to during
C5 and C6, without any instruction of the lower priority rou-
tine having been executed.
The processor responds to an interrupt request by execut-
ing a hardware-generated LCALL to the appropriate
service routine. LCALL pushes the contents of the program
counter onto the stack and reloads the PC with an address
that depends on the source of the interrupt, as shown in
Table 9.
In some cases LCALL clears the flags that triggered the
interrupt. It clears an external interrupt flag (IE0 or IE1) only
if it was edge-triggered. LCALL never clears the serial port
or Timer 2 flags. This has to be done by the application
software.
Execution of the interrupt service routine continues from
the interrupt vector address until the RETI instruction is
encountered. The RETI instruction informs the processor
that the interrupt service routine has terminated, then pops
the top two bytes from the stack and reloads the program
counter with them. Execution of the interrupted program
continues from where it left off.
A simple RET instruction would also return execution to the
interrupted program, but it would leave the interrupt control
system thinking that an interrupt was still in progress.
External Interrupts
The external sources can be programmed to level-sensitive
or edge-sensitive by setting or clearing bit IT0 or IT1 in
Register TCON. If ITx = 0, then external interrupt x is trig-
gered by a detected low at the INTx pin. But if ITx = 1,
external interrupt x is edge-triggered. In this case if the
INTx pin shows a high in one cycle and a low in the next
one, the interrupt request flag IEx in TCON is set. Flag bit
IEx then requests the interrupt.
Since the external interrupt pins are sampled only once in
each machine cycle, an input high or low should hold for at
least 12 oscillator periods to guarantee sampling. If the
external interrupt is edge-triggered, the external source has
to hold the request pin high for at least one machine cycle,
and then low for at least one machine cycle to ensure that
the transition is detected. IEx is automatically cleared by
the AT_8032 when the service routine is called.
If the external interrupt is level-sensitive, the external
source has to hold the request active until the requested
interrupt is actually generated. It must then deactivate the
request before the interrupt service routine is completed; or
else another interrupt will be generated.
Interrupt Response Time
The INT0 and INT1 levels are polled and latched into the
interrupt flags IE0 and IE1 at S5P2 of every machine cycle.
Timer 2 flag EXF2 and the serial port flags RI and TI are set
at S5P2 the same way. The circuit polls the values until the
next machine cycle.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The circuit
polls the values until the next machine cycle.
However, the Timer 2 flag TF2 is set at S2P2 and the cir-
cuit polls the values in the same cycle in which the timer
overflow occurs.
If an interrupt request is active and conditions are right for it
to be acknowledged, it will be the next to be executed. The
hardware subroutine call takes two cycles. Thus a mini-
mum of three cycles are necessary between the activation
of an external interrupt request and the beginning of execu-
tion of the corresponding interrupt handling routine.
A longer response time is required under any of the three
following conditions. If an interrupt of equal or higher prior-
ity level is in progress, the additional wait time depends of
the length of its interrupt service routine. If the instruction in
progress is not in its final cycle, it must be completed. The
maximum wait time in this case is three cycles; the longest
instructions are only four cycles long (MUL and DIV). If the
instruction in progress is RETI or an access to EI or IP, the
additional wait time cannot be more than five cycles.
This means that in a single-interrupt situation, the response
time is always between three and nine cycles.
Table 9.
Interrupt Vector Addresses
Source
Vector Address
IE0
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI + TI
0023H
TF2 + EXF2
002BH
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