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參數(shù)資料
| 型號(hào)： | AT_8032 |
| 廠商： | Atmel Corp. |
| 英文描述： | 8-bit Embedded Microcontroller Core(8位嵌入式基于工業(yè)標(biāo)準(zhǔn)軟件兼容的微控制器) |
| 中文描述： | 8位嵌入式微控制器核心（8位嵌入式基于工業(yè)標(biāo)準(zhǔn)軟件兼容的微控制器） |
| 文件頁數(shù)： | 27/39頁 |
| 文件大?。?/td> | 532K |
| 代理商： | AT_8032 |
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AT_8032 Core
27
set RI, will be generated if, and only if, the following condi-
tions are met at the time the final shift pulse is generated:
1.
RI = 0, and
2.
SM2 = 0 or the received 9th data bit = 1
If neither of these conditions is met, the received frame is
irretrievably lost, and RI is not set. If both conditions are
met, the 9th data bit received goes into RB8, and the first 8
data bits go into SBUF. One bit time later, whether the
above conditions were met or not, the unit starts looking for
1-to-0 transition at the RXD input.
Note that the value of the received stop bit is irrelevant to
SBUF and RB8.
Interrupts
The external interrupts INT0 and INT1 are generated by the
flags IE0 and IE1 in the register TCON. They can be level-
sensitive or edge-sensitive. This is determined by the bits
IT0 and IT1 in register TCON. When an external interrupt is
generated, its flag is cleared by the hardware when the ser-
vice routine is vectored to only if the interrupt is edge-
sensitive. When the external requesting source controls the
request flag, rather than on-chip hardware, it means that
the interrupt is level-sensitive.
The logical OR of RI and TI generates the UART interrupt.
Neither of these flags is cleared by hardware when the ser-
vice routine is vectored to. The interrupt service routine has
to determine if it is RI or TI that is generating the interrupt,
and the flag has to be cleared by software.
TF0 and TF1 generate the Timer 0 and Timer 1 interrupts.
These are set by a rollover in their respective
Timer/Counter registers (except Timer 0 in Mode 3). When
a timer interrupt is generated, its flag is cleared by the on-
chip hardware when the service routine is vectored to. The
Timer 2 interrupt is generated by the logical OR of TF2 and
EXF2. Neither of these flags is cleared by hardware when
the service routine is vectored to. The service routine has
to determine if it is TF2 or EXF2 that is generating the inter-
rupt, and the flag has to cleared by software.
All of the bits that generate interrupts can be set or cleared
by software, with the same results as when set or cleared
by hardware. That is, interrupts can be generated or pend-
ing interrupts can be cancelled by software.
Setting or clearing a bit in Special Function Register IE
enables or disables each of these interrupt sources individ-
ually. EA (also in IE) is a global disable bit which disables
all interrupts at once.
Interrupt Priority
Each interrupt can be assigned one of two levels of priority
by setting or clearing a bit in Special Function Register IP.
A low-priority interrupt can be interrupted by a higher-prior-
ity interrupt. But a low-priority cannot be interrupted by
another low-priority interrupt. A high-priority interrupt can-
not be interrupted by any other interrupt source.
If two interrupts arrive simultaneously, the higher-priority
one will be served first. If these interrupts have the same
priority level, an internal polling sequence chooses which
one will be served first. Table 8 shows the priorities within
this polling sequence.
Interrupt Handling
The interrupt flags are sampled at S5P2 of every machine
cycle. The samples are polled during the following machine
cycles (the Timer 2 interrupt cycle is different, as described
in the Response Time Section). If one of the interrupt flags
is set, the polling cycle finds it and the interrupt system
generates an LCALL to the appropriate service routine,
provided that this LCALL is not blocked by any of the fol-
lowing conditions:
1.
An interrupt of equal or higher priority level is
already in progress;
2.
The current (polling) cycle is not the final cycle in
the execution of the instruction in progress;
3.
The instruction in progress is RETI or any write to
the IE or IP registers.
Any of these three conditions blocks the generation of the
LCALL to the interrupt service routine. Condition 2 guaran-
tees that the instruction in progress is completed before
any other service routine starts. Conditions 3 guarantees
that if the instruction in progress is RETI or any access to
IE or IP, then at least one more instruction will be executed
before any interrupt service routine is vectored to.
The polling loop is repeated during each machine cycle,
and the values polled are those that were present at S5P2
of the previous machine cycle. If an interrupt flag is active
but not being responded to due to one of the above condi-
tions, and is not still active when the blocking condition is
removed, then the denied interrupt is not serviced.
Table 8.
Interrupt Priorities
Source
Priority Within Level
1. IE0
Highest
2. TF0
3. IE1
4. TF1
5. RI + TI
6. TF2 + EXF2
Lowest
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