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參數(shù)資料
| 型號： | AT_8032 |
| 廠商： | Atmel Corp. |
| 英文描述： | 8-bit Embedded Microcontroller Core(8位嵌入式基于工業(yè)標準軟件兼容的微控制器) |
| 中文描述： | 8位嵌入式微控制器核心（8位嵌入式基于工業(yè)標準軟件兼容的微控制器） |
| 文件頁數(shù)： | 33/39頁 |
| 文件大?。?/td> | 532K |
| 代理商： | AT_8032 |
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AT_8032 Core
33
IE: Interrupt Enable Register
The interrupt enable register (IE) is bit addressable. If a bit is 0, the corresponding interrupt is disabled. If the bit is 1, the
corresponding interrupt is enabled.
Priority Within Level
Priority within level is used only to resolve simultaneous
interrupt requests at the same priority level.
From high to low priority, the interrupt sources are as
follows:
1.
IE0
2.
TF0
3.
IE1
4.
TF1
5.
ES: RI or TI
6.
ET2 + EXF2
Interrupt Use
Interrupts must be used in the following way:
1.
Set the EA (enable all) bit in the IE Register to 1.
2.
Set the corresponding individual interrupt enable bit
in the IE Register to 1.
3.
Place the interrupt service routine starting at the
corresponding vector address of that interrupt.
In addition, for external interrupts, pins INT0 and INT1
(P3.2 and P3.3) must be set to 1, and depending on
whether the interrupt is to be level- or edge-sensitive, bits
IT0 or IT1 in the TCON Register should be set to 0 or 1:
ITx = 0 level activated
ITx = 1 transition activated
Table 16.
Interrupt Enable Register
MSB
LSB
EA
X
ET2
ES
ET1
EX1
ET0
EX0
Table 17.
Interrupt Enable Register Bit Functions
Symbol
Position
Function
EA
IE7
Disable all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or clearing its enable bit.
IE6
Reserved
ET2
IE5
Enables or disables the Timer 2 Overflow or Capture interrupt. If ET2 = 0, the Timer 2 Interrupt is
disabled.
ES
IE4
Enables or disables the serial port (UART) Interrupts RI and TI. If ES = 0, the serial port Interrupt
is disabled.
ET1
IE3
Enables or disables Timer 1 Overflow Interrupt. If ET1 = 0, the Timer 1 Interrupt is disabled.
EX1
IE2
Enables or disables External Interrupt 1. If EX1 = 0, External Interrupt 1 is disabled.
ET0
IE1
Enables or disables Timer 0 Overflow Interrupt. If ET0 = 0, the Timer 0 Interrupt is disabled.
EX0
IE0
Enables or disables External Interrupt 0. If EX0 = 0, External Interrupt 0 is disabled.
Table 18.
Interrupt Service Routine Addresses
Interrupt Source
Vector Address
IE0
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI & TI
0023H
ET2 + EXF2
002BH
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