
AT_8032 Core
19
external for different ports. For Ports 1, 2 and 3, the pin is
pulled high by the external pull-up, but can be pulled low by
an external source. If the port is used as an output, the port
output pulls the pin low and the external pull-up pulls the
pin high.
All the port latches in the AT_8032 have ones written on
them by the reset function. If a zero is subsequently written
to a latch, it can be reconfigured as input by writing a one
on it.
Writing to a Port
In the execution of an instruction that modifies the value of
a port latch, the new value arrives at the latch during S6P2
of the final machine cycle. However, port latches are only
tested by their output buffer during phase 1 of any clock
period. Consequently, the new value in port latch does not
appear at the output pin until the next phase 1, which will
be at S1P1 of the next machine cycle.
Read-Modify-Write Feature
Some instructions read the latch at the same time they are
reading a port. Others read the pin. The instructions that
read the latch read a value, but can also modify and rewrite
it. They are called the
“
read-modify-write
”
instructions.
When the destination operand is a port, the instructions
read the latch rather than the pin.
Bi-directional Input/Output Implementation
As no I/O cells are included in the design, all bi-directional
lines are split into input and output sections, and have
associate control lines for enabling and disabling tristate
buffers where appropriate. There is an enable for each of
the port outputs. This is to allow individual implementation
of the
“
quasi bi-directional
”
pins feature of the original
device. If the port goes to external (in a bi-directional port
configuration), the ports must have an external pull-up.
For the port P1, P2, P3 (except P3.0), the enable goes to
low when the port outputs the data 0.
For port P3.0 an additional condition is present on the
enable (mode 0 for the UART).
For port P0, only one control signal is used for all bits
because this port handles the low byte of the program
address or the program instruction itself (Opcode, 2nd
byte, 3rd byte). This port is time-multiplexed. When the
control signal is high, P0 outputs the program address. To
obtain a full control on P0, the WR signal must be associ-
ated with the signal control (instruction MOV X).
Port P2 handles the high byte of the program memory
address for all instructions except the MOV X instructions;
and for the MOV X instructions, P2 outputs the high byte of
the data pointer (dph) or P2 SFR.
Table 5.
Read-Modify-Write Instructions
Instruction
Description
Example
ANL
Logical AND
ANL P1, A
ORL
Logical OR
ORL P2, A
XRL
Logical EX-OR
XRL P3, A
JBC
Jump if bit = 1 and clear
bit
JBC P1.1, LABEL
CPL
Complement bit
CPL P3.0
INC
Increment
INC P2
DEC
Decrement
DEC P2
DJNZ
Decrement and jump if
not zero
DJNZ P3, LABEL
MOV, PX.Y,
C
Move carry bit to bit Y of
Port X
CLR PX.Y
Clear bit Y of Port X
SETB PX.Y
Set bit Y of Port X
Table 5.
Read-Modify-Write Instructions (Continued)
Instruction
Description
Example