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| 型號： | ARM60 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁數(shù)： | 93/120頁 |
| 文件大?。?/td> | 1275K |
| 代理商： | ARM60 |
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Boundary Scan Test Interface
89
8.0 Boundary Scan Test Interface
The boundary-scan interface conforms to the IEEE Std. 1149.1- 1990, Standard Test Access Port and
Boundary-Scan Architecture (please refer to this standard for an explanation of the terms used in this
section and for a description of the TAP controller states.)
8.1 Overview
The boundary-scan interface provides a means of testing the core of the device when it is fitted to a circuit
board, and a means of driving and sampling all the external pins of the device irrespective of the core state.
This latter function permits testing of both the device's electrical connections to the circuit board, and (in
conjunction with other devices on the circuit board having a similar interface) testing the integrity of the
circuit board connections between devices. The interface intercepts all external connections within the
device, and each such òcelló is then connected together to form a serial register (the boundary scan register).
The whole interface is controlled via 5 dedicated pins:
Access Port (TAP) Controller State Transitions
shows the state transitions that occur in the TAP controller.
TDI
,
TMS
,
TCK
,
nTRST
and
TDO
.
Figure 32: Test
Figure 32: Test Access Port (TAP) Controller State Transitions
Select-IR-Scan
Capture-IR
tms=0
Shift-IR
tms=0
Exit1-IR
tms=1
Pause-IR
tms=0
Exit2-IR
tms=1
Update-IR
tms=1
tms=0
tms=0
tms=1
tms=1
tms=0
Select-DR-Scan
Capture-DR
tms=0
Shift-DR
tms=0
Exit1-DR
tms=1
Pause-DR
tms=0
Exit2-DR
tms=1
Update-DR
tms=1
Test-Logic Reset
Run-Test/Idle
tms=0
tms=1
tms=0
tms=0
tms=0
tms=1
tms=1
tms=0
tms=1
tms=1
tms=1
tms=1
tms=1
tms=0
tms=0
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