參數(shù)資料
型號： ARM60
廠商： Zarlink Semiconductor Inc.
英文描述： Low power, general purpose 32-bit RISC microprocessor
中文描述： 低功耗，通用32位RISC微處理器
文件頁數(shù)： 53/120頁
文件大?。?/td> 1275K
代理商： ARM60
Instruction Set - SWP
49
4.9.3 Data
Aborts
If the address used for the swap is unacceptable to a memory management system, the internal MMU or
external memory manager can flag the problem by driving ABORT HIGH. This can happen on either the
read or the write cycle (or both), and in either case, the Data Abort trap will be taken. It is up to the system
software to resolve the cause of the problem, then the instruction can be restarted and the original program
continued.
Because no base register write-back is allowed, the behaviour of an
aborted SWP instruction is the same
regardless of the state of the
LATEABT
control signal.
4.9.4 Instruction Cycle Times
Swap instructions take 1S + 2N +1I incremental cycles to execute, where S,N and I are as defined in section
5.1 Cycle types on page 65.
4.9.5 Assembler syntax
<SWP>{cond}{B} Rd,Rm,[Rn]
{cond} - two-character condition mnemonic, see
Figure 6: Condition Codes
{B} - if B is present then byte transfer, otherwise word transfer
Rd,Rm,Rn are expressions evaluating to valid register numbers
4.9.6 Examples
SWP
R0,R1,[R2]
; load R0 with the contents of R2, and
; store R1 at R2
SWPB
R2,R3,[R4]
; load R2 with the byte at R4, and
; store bits 0 to 7 of R3 at R4
SWPEQ
R0,R0,[R1]
; conditionally swap the contents of R1
; with R0
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