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| 型號： | ARM60 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁數(shù)： | 34/120頁 |
| 文件大?。?/td> | 1275K |
| 代理商： | ARM60 |
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P60ARM-B
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4.5 PSR Transfer (MRS, MSR)
The instruction is only executed if the condition is true. The various conditions are defined at the beginning
of this chapter.
The MRS and MSR instructions are formed from a subset of the Data Processing operations and are
implemented using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is
shown in
Figure 15: PSR Transfer
.
These instructions allow access to the CPSR and SPSR registers. The MRS instruction allows the contents of
the CPSR or SPSR_<mode> to be moved to a general register. The MSR instruction allows the contents of a
general register to be moved to the CPSR or SPSR_<mode> register.
The MSR instruction also allows an immediate value or register contents to be transferred to the condition
code flags (N,Z,C and V) of CPSR or SPSR_<mode> without affecting the control bits. In this case, the top
four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the
relevant PSR.
4.5.1 Operand restrictions
In User mode, the control bits of the CPSR are protected from change, so only the condition code flags of
the CPSR can be changed. In other (privileged) modes the entire CPSR can be changed.
The SPSR register which is accessed depends on the mode at the time of execution. For example, only
SPSR_fiq is accessible when the processor is in FIQ mode.
R15 shall not be specified as the source or destination register.
A further restriction is that no attempt shall be made to access an SPSR in User mode, since no such register
exists.
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