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參數資料
| 型號： | ARM60 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁數： | 31/120頁 |
| 文件大?。?/td> | 1275K |
| 代理商： | ARM60 |
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Instruction Set - Shifts
27
Figure 13: Rotate Right
The form of the shift field which might be expected to give ROR #0 is used to encode a special function of
the barrel shifter, rotate right extended (RRX). This is a rotate right by one bit position of the 33 bit quantity
formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in
Figure
14: Rotate Right Extended
.
Figure 14: Rotate Right Extended
Register specified shift amount
Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any
general register other than R15.
If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of
the CPSR C flag will be passed on as the shifter carry output.
If the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified
shift with the same value and shift operation.
If the value in the byte is 32 or more, the result will be a logical extension of the shift described above:
(1)
LSL by 32 has result zero, carry out equal to bit 0 of Rm.
(2)
LSL by more than 32 has result zero, carry out zero.
(3)
LSR by 32 has result zero, carry out equal to bit 31 of Rm.
(4)
LSR by more than 32 has result zero, carry out zero.
contents of Rm
value of operand 2
31
0
carry out
5 4
contents of Rm
value of operand 2
31
0
carry
out
1
C
in
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