參數(shù)資料
型號(hào): ARM60
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁(yè)數(shù): 91/120頁(yè)
文件大?。?/td> 1275K
代理商: ARM60
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Instruction Cycle Operations
87
7.15 UndeTned instructions and coprocessor absent
When a coprocessor detects a coprocessor instruction which it cannot perform, and this must include all
undefined instructions, it must not drive
CPA
or
CPB
LOW. These will remain HIGH, causing the
undefined instruction trap to be taken. Cycle timings are shown in
Table 21: Undefined Instruction Cycle
Operations
.
7.16 Unexecuted instructions
Any instruction whose condition code is not met will fail to execute. It will add one cycle to the execution
time of the code segment in which it is embedded (see
Table 22: Unexecuted Instruction Cycle Operations
).
Cycle
Address
nBW
nRW
Data
nMREQ
SEQ
nOPC
nCPI
CPA
CPB
ready
1
pc+8
1
0
(pc+8)
1
1
0
0
0
0
2
pc+12
1
1
Rd
0
0
1
1
1
1
pc+12
not ready
1
pc+8
1
0
(pc+8)
1
0
0
0
0
1
2
pc+8
1
0
-
1
0
1
0
0
1
pc+8
1
0
-
1
0
1
0
0
1
n
pc+8
1
0
-
1
1
1
0
0
0
n+1
pc+12
1
1
Rd
0
0
1
1
1
1
pc+12
Table 20: Coprocessor register transfer (Store to coprocessor)
Cycle
Address
nBW
nRW
Data
nMREQ
SEQ
nOPC
nCPI
CPA
CPB
1
pc+8
1
0
(pc+8)
1
0
0
0
1
1
2
pc+8
1
0
-
0
0
0
1
1
1
3
Xn
1
0
(Xn)
0
1
0
1
1
1
4
Xn+4
1
0
(Xn+4)
0
1
0
1
1
1
Xn+8
Table 21: Undefined Instruction Cycle Operations
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