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參數(shù)資料
| 型號： | ARM60 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁數(shù)： | 87/120頁 |
| 文件大?。?/td> | 1275K |
| 代理商： | ARM60 |
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Instruction Cycle Operations
83
7.10 Coprocessor data operation
A coprocessor data operation is a request from ARM60 for the coprocessor to initiate some action. The
action need not be completed for some time, but the coprocessor must commit to doing it before driving
CPB
LOW.
If the coprocessor can never do the requested task, it should leave
CPA
and
CPB
HIGH. If it can do the task,
but can't commit right now, it should drive
CPA
LOW but leave
CPB
HIGH until it can commit. ARM60
will busy-wait until
CPB
goes LOW. The cycle timings are shown in
Table 16: Coprocessor Data Operation
Instruction Cycle Operations
.
7.11 Coprocessor data transfer (from memory to coprocessor)
Here the coprocessor should commit to the transfer only when it is ready to accept the data. When
CPB
goes
LOW, ARM60 will produce addresses and expect the coprocessor to take the data at sequential cycle rates.
The coprocessor is responsible for determining the number of words to be transferred, and indicates the last
transfer cycle by driving
CPA
and
CPB
HIGH.
ARM60 spends the first cycle (and any busy-wait cycles) generating the transfer address, and performs the
write-back of the address base during the transfer cycles. The cycle timings are shown in
Table 17:
Coprocessor Data Transfer Instruction Cycle Operations
.
Cycle
Address
nBW
nRW
Data
nMREQ
SEQ
nOPC
nCPI
CPA
CPB
ready
1
pc+8
1
0
(pc+8)
0
0
0
0
0
0
pc+12
not ready
1
pc+8
1
0
(pc+8)
1
0
0
0
0
1
2
pc+8
1
0
-
1
0
1
0
0
1
pc+8
1
0
-
1
0
1
0
0
1
n
pc+8
1
0
-
0
0
1
0
0
0
pc+12
Table 16:
Coprocessor Data Operation Instruction Cycle Operations
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相關(guān)代理商/技術(shù)參數(shù) |
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