- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378406 > ARM60 (Zarlink Semiconductor Inc.) Low power, general purpose 32-bit RISC microprocessor PDF資料下載
參數(shù)資料
| 型號(hào)： | ARM60 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁數(shù)： | 10/120頁 |
| 文件大?。?/td> | 1275K |
| 代理商： | ARM60 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁
P60ARM-B
6
DBE
I
Data bus enable. When
When
DBE
goes HIGH these output drivers are enabled.
DMA and so on.
DBE
is LOW the write data register output drivers are disabled.
DBE
facilitates data bus sharing for
LATEABT
I
Late
HIGH (Late
back. When it is LOW (Early abort) the modified base register is not written back.
must not be changed during the execution of a data access instruction where abort is active.
It is recommended that the Late
abort scheme be used where possible as this scheme will be
used in future ARM processors.
abort. This signal controls the action of the processor on an
abort) the modified base register of an
abort exception. When it is
aborted LDR or STR instruction is written
LATEABT
LOCK
OS8
Locked operation. When
access, and the memory controller must wait until
device to access the memory.
the duration of the locked memory accesses. It is active only during the data swap (SWP)
instruction.
LOCK
is HIGH, the processor is performing a òl(fā)ockedó memory
LOCK
goes LOW before allowing another
LOCK
changes while
MCLK
is HIGH, and remains HIGH for
MCLK
I
Memory clock input. This clock times all ARM60 memory accesses and internal operations.
The clock has two distinct phases -
phase 1
in which
MCLK
(and
nWAIT
) is HIGH. The clock may be stretched indefinitely in either phase to
allow access to slow peripherals or memory. Alternatively, the
with a free running
MCLK
to achieve the same effect.
MCLK
is LOW and
phase 2
in which
nWAIT
input may be used
nBW
OS8
Not byte/word. This is an output signal used by the processor to indicate to the external
memory system when a data transfer of a byte length is required. The signal is HIGH for
word transfers and LOW for byte transfers and is valid for both read and write cycles. The
signal will become valid during phase 2 of the cycle before the one in which the transfer will
take place. It will remain stable throughout phase 1 of the transfer cycle.
nCPI
O4
Not Coprocessor instruction. When ARM60 executes a coprocessor instruction, it will take
this output LOW and wait for a response from the coprocessor. The action taken will depend
on this response, which the coprocessor signals on the
CPA
and
CPB
inputs.
nFIQ
I
Not fast interrupt request. This is an asynchronous interrupt request to the processor which
causes it to be interrupted if taken LOW when the appropriate enable in the processor is
active. The signal is level sensitive and must be held LOW until a suitable response is
received from the processor.
nIRQ
I
Not interrupt request. As
to interrupt the processor when the appropriate enable is active.
nFIQ
, but with lower priority. May be taken LOW asynchronously
nMREQ
O4
Not memory request. This signal, when LOW, indicates that the processor requires memory
access during the following cycle. The signal becomes valid during phase 1, remaining valid
through phase 2 of the cycle preceding that to which it refers.
nOPC
O4
Not op-code fetch. When LOW this signal indicates that the processor is fetching an
instruction from memory; when HIGH, data (if present) is being transferred. The signal
becomes valid during phase 2 of the previous cycle, remaining valid through phase 1 of the
referenced cycle.
Name
Type
Description
Table 1: Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ARM610 | General purpose 32-bit microprocessor |
| ARM7TDMI | 32-Bit Advanced RISC Machines(ARM) Microprocessor Core(32位ARM微處理器內(nèi)核芯片) |
| ART10012T | 28V Input, Triple Output / HYBRID - HIGH RELIABILITY RADIATION HARDENED DC/DC CONVERTER |
| ART10015T | 28V Input, Triple Output / HYBRID - HIGH RELIABILITY RADIATION HARDENED DC/DC CONVERTER |
| ART2812T | 28V Input, Triple Output / HYBRID - HIGH RELIABILITY RADIATION HARDENED DC/DC CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ARM607 | 制造商:Master Appliance Corp 功能描述:Armature, With Retaining Rings, 120V (HG 制造商:Master Appliance Corp 功能描述:Armature, With Retaining Rings, 120V (HG-751B) |
| ARM-607 | 制造商:Master Appliance Corp 功能描述:Nozzle Shield; HG-751B heat gun 制造商:Master Appliance 功能描述:Heat Gun,Armature W/Retaining Ring For Hg-751B 120V, Hg-501A-D |
| ARM610 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| ARM7-009 | 制造商:Gravitech 功能描述:ARM7 LPC2378 W/2.8" TCH SCRN LCD BLU |
| ARM720T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。