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參數(shù)資料
| 型號： | ARM60 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁數(shù)： | 69/120頁 |
| 文件大?。?/td> | 1275K |
| 代理商： | ARM60 |
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Memory Interface
65
5.0 Memory Interface
ARM60 communicates with its memory system via a bidirectional data bus (
address bus specifies the memory location to be used for the transfer, and the
direction of transfer (ARM60 to memory or memory to ARM60). Control signals give additional
information about the transfer cycle, and in particular they facilitate the use of DRAM page mode where
applicable. Interfaces to static RAM based memories can also be interfaced to and, in general, they are much
simpler than the DRAM interface described here.
D[31:0]
). A separate 32 bit
nRW
signal gives the
5.1 Cycle types
All memory transfer cycles can be placed in one of four categories:
(1)
Non-sequential cycle. ARM60 requests a transfer to or from an address which is unrelated to the
address used in the preceding cycle.
(2)
Sequential cycle. ARM60 requests a transfer to or from an address which is either the same as the
address in the preceding cycle, or is one word after the preceding address.
(3)
Internal cycle. ARM60 does not require a transfer, as it is performing an internal function and no
useful prefetching can be performed at the same time.
(4)
Coprocessor register transfer. ARM60 wishes to use the data bus to communicate with a
coprocessor, but does not require any action by the memory system.
These four classes are distinguishable to the memory system by inspection of the
lines (see
Table 6: Memory Cycle Types
). These control lines are generated during phase 1 of the cycle before
the cycle whose characteristics they forecast, and this pipelining of the control information gives the
memory system sufficient time to decide whether or not it can use a page mode access.
nMREQ
and
SEQ
control
Figure 29: ARM Memory Cycle Timing
DRAM address strobes (
cycle is longer than the other cycles. This is to allow for the DRAM precharge and row access time, and is
not an ARM60 requirement.
shows the pipelining of the control signals, and suggests how the
nCAS
) might be timed to use page mode for S-cycles. Note that the N-
nRAS
and
nMREQ
SEQ
Cycle type
0
0
Non-sequential cycle (N-cycle)
0
1
Sequential cycle (S-cycle)
1
0
Internal cycle (I-cycle)
1
1
Coprocessor register transfer (C-cycle)
Table 6: Memory Cycle Types
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相關(guān)代理商/技術(shù)參數(shù) |
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