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參數(shù)資料
| 型號(hào)： | ARM60 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁(yè)數(shù)： | 21/120頁(yè) |
| 文件大?。?/td> | 1275K |
| 代理商： | ARM60 |
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Programmer's Model
17
3.4.8 Interrupt Latencies
The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take
to pass through the synchroniser (
Tsyncmax
), plus the time for the longest instruction to complete (
longest instruction is an LDM which loads all the registers including the PC), plus the time for the data abort
entry (
Texc
), plus the time for FIQ entry (
Tfiq
). At the end of this time ARM60 will be executing the
instruction at 0x1C.
Tldm
, the
Tsyncmax
therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20
MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ
has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The
minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser
(
Tsyncmin
) plus
Tfiq
. This is 4 processor cycles.
is 3 processor cycles,
Tldm
is 20 cycles,
Texc
is 3 cycles, and
Tfiq
is 2 cycles. The total time is
To reduce the interupt latency, Tldm can be reduced by using an option in the complier which splits LDM
instructions so that it will only load or store a user defined number (between 3 and 16) of registers at any
one time.
If this option is used, then the MUL or MLA instruction can potentially become the longest taking up to 17
cycles, depending on the data being manipulated.
3.5 Reset
When the
nRESET
signal goes LOW, ARM60 abandons the executing instruction and then continues to
fetch instructions from incrementing word addresses.
When
nRESET
goes HIGH again, ARM60 does the following:
(1)
Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them.
The value of the saved PC and CPSR is not defined.
(2)
Forces M[4:0]=10011 (Supervisor mode) and sets the I and F bits in the CPSR.
(3)
Forces the PC to fetch the next instruction from address 0x00
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