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參數(shù)資料
| 型號(hào)： | ARM60 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁(yè)數(shù)： | 5/120頁(yè) |
| 文件大?。?/td> | 1275K |
| 代理商： | ARM60 |
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Introduction
1
1.0 Introduction
The ARM60 is part of the Advanced RISC Machines (ARM) family of general purpose 32-bit
microprocessors, which offer very low power consumption and price for high performance devices. The
architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler in comparison with microprogrammed Complex Instruction
Set Computers. This results in a high instruction throughput and impressive real-time interrupt response
from a small and cost-effective chip.
The instruction set comprises eleven basic instruction types:
￥
Two of these make use of the on-chip arithmetic logic unit, barrel shifter and multiplier to perform
high-speed operations on the data in a bank of 31 registers, each 32 bits wide;
￥
Three classes of instruction control data transfer between memory and the registers, one optimised
for flexibility of addressing, another for rapid context switching and the third for swapping data;
￥
Three instructions control the flow and privilege level of execution; and
￥
Three types are dedicated to the control of external coprocessors which allow the functionality of
the instruction set to be extended off-chip in an open and uniform way.
The ARM instruction set is a good target for compilers of many different high-level languages. Where
required for critical code segments, assembly code programming is also straightforward, unlike some RISC
processors which depend on sophisticated compiler technology to manage complicated instruction
interdependencies.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously.
Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is
being fetched from memory.
The memory interface has been designed to allow the performance potential to be realised without
incurring high costs in the memory system. Speed critical control signals are pipelined to allow system
control functions to be implemented in standard low-power logic, and these control signals facilitate the
exploitation of the fast access modes offered by industry standard dynamic RAMs.
ARM60 has a 32 bit address bus. All ARM processors share the same instruction set, and ARM60 can be
configured to use a 26 bit address bus for backwards compatibility with earlier processors.
ARM60 is a fully static CMOS implementation of the ARM which allows the clock to be stopped in any part
of the cycle with extremely low residual power consumption and no loss of state.
Notation:
0x
BOLD
binary
- marks a Hexadecimal quantity
- external signals are shown in bold capital letters
- where it is not clear that a quantity is binary it is followed by the word binary
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ARM610 | General purpose 32-bit microprocessor |
| ARM7TDMI | 32-Bit Advanced RISC Machines(ARM) Microprocessor Core(32位ARM微處理器內(nèi)核芯片) |
| ART10012T | 28V Input, Triple Output / HYBRID - HIGH RELIABILITY RADIATION HARDENED DC/DC CONVERTER |
| ART10015T | 28V Input, Triple Output / HYBRID - HIGH RELIABILITY RADIATION HARDENED DC/DC CONVERTER |
| ART2812T | 28V Input, Triple Output / HYBRID - HIGH RELIABILITY RADIATION HARDENED DC/DC CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ARM607 | 制造商:Master Appliance Corp 功能描述:Armature, With Retaining Rings, 120V (HG 制造商:Master Appliance Corp 功能描述:Armature, With Retaining Rings, 120V (HG-751B) |
| ARM-607 | 制造商:Master Appliance Corp 功能描述:Nozzle Shield; HG-751B heat gun 制造商:Master Appliance 功能描述:Heat Gun,Armature W/Retaining Ring For Hg-751B 120V, Hg-501A-D |
| ARM610 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| ARM7-009 | 制造商:Gravitech 功能描述:ARM7 LPC2378 W/2.8" TCH SCRN LCD BLU |
| ARM720T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip |
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