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參數(shù)資料
| 型號(hào)： | Alpha 21164 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Alpha Microprocessor(64位微處理器) |
| 中文描述： | 阿爾法微處理器（64位微處理器） |
| 文件頁(yè)數(shù)： | 9/115頁(yè) |
| 文件大?。?/td> | 846K |
| 代理商： | ALPHA 21164 |
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Microarchitecture
9
Cache Control and Bus Interface Unit
By the time the load instruction arrives at the Dcache the second time, the conflicting
store instruction has written the Dcache and the load instruction is executed nor-
mally.
Replay traps can be avoided by scheduling the load instruction to issue three cycles
after the store instruction. If the load instruction is scheduled to issue two cycles after
the store instruction, then it will be issue-stalled for one cycle.
3.4.4 Write Buffer
The MTU also contains a write buffer that has six 32-byte entries. The write buffer
provides a finite, high-bandwidth resource for receiving store data to minimize the
number of CPU stall cycles.
3.5 Cache Control and Bus Interface Unit
The cache control and bus interface unit (CBU) processes all accesses sent by the
MTU and implements all memory-related external interface functions, particularly
the coherence protocol functions for write-back caching. It controls the second-level
cache (Scache) and the optional board-level backup cache (Bcache). The CBU han-
dles all instruction and primary Dcache read misses, performs the function of writing
data from the write buffer into the shared coherent memory subsystem, and has a
major role in executing the Alpha memory barrier (MB) instruction. The CBU also
controls the 128-bit bidirectional data bus, address bus, and I/O control.
3.6 Cache Organization
The 21164 has three onchip caches—a primary L1 data cache, a primary L1 instruc-
tion cache, and a second-level L2 combined data and instruction cache. All memory
cells in the onchip caches are fully static, 6-transistor, CMOS structures.
The 21164 also provides control for an optional board-level, external L3 cache.
3.6.1 Data Cache
The data cache (Dcache) is a dual-read-ported, single-write-ported, 8KB cache. It is
a write-through, read-allocate, direct-mapped, physical cache with 32-byte blocks.
3.6.2 Instruction Cache
The instruction cache (Icache) is an 8KB, virtual, direct-mapped cache with 32-byte
blocks. Each block tag contains:
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