參數(shù)資料
型號(hào)： Alpha 21164
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Alpha Microprocessor(64位微處理器)
中文描述： 阿爾法微處理器（64位微處理器）
文件頁數(shù)： 7/115頁
文件大?。?/td> 846K
代理商： ALPHA 21164
Microarchitecture
7
Floating-Point Execution Unit
An integer multiplier
The IEU also includes the 40-entry, 64-bit integer register file (IRF) that contains the
32 integer registers defined by the Alpha architecture and 8 PALshadow registers.
The register file has four read ports and two write ports, which provide operands to
both integer execution pipelines and accept results from both pipes. The register file
also accepts load instruction results (memory data) on the same two write ports.
3.3 Floating-Point Execution Unit
The onchip, pipelined floating-point unit (FPU) can execute both IEEE and VAX
floating-point instructions. The 21164 supports IEEE S_floating and T_floating data
types, and all rounding modes. It also supports VAX F_floating and G_floating data
types, and provides limited support for the D_floating format. The FPU contains:
A 32-entry, 64-bit floating-point register file (FRF).
A user-accessible control register.
A floating-point multiply pipeline.
A floating-point add pipeline—The floating-point divide unit is associated with
the floating-point add pipeline but is not pipelined.
The FPU can accept two instructions every cycle, with the exception of floating-
point divide instructions. The result latency for nondivide, floating-point instructions
is four cycles.
3.4 Memory Address Translation Unit
The memory address translation unit (MTU) contains three major sections:
Data translation buffer (dual ported)
Miss address file (MAF)
Write buffer address file
The MTU receives up to two virtual addresses every cycle from the IEU. The trans-
lation buffer generates the corresponding physical addresses and access control
information for each virtual address. The 21164 implements a 43-bit virtual address
and a 40-bit physical address.
The MTU can perform read and write operations to/from memory on byte, word,
longword, and quadword boundaries.
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